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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa20dffd6a6sm61162066b.99.2024.11.14.05.03.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Nov 2024 05:03:24 -0800 (PST) Message-ID: <26943ea3-109c-473d-818b-2a08dba859ab@oss.qualcomm.com> Date: Thu, 14 Nov 2024 14:03:20 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] arm64: dts: qcom: qcs8300: enable pcie0 for QCS8300 To: Dmitry Baryshkov , Ziyue Zhang Cc: vkoul@kernel.org, kishon@kernel.org, robh+dt@kernel.org, manivannan.sadhasivam@linaro.org, bhelgaas@google.com, kw@linux.com, lpieralisi@kernel.org, quic_qianyu@quicinc.com, conor+dt@kernel.org, neil.armstrong@linaro.org, andersson@kernel.org, konradybcio@kernel.org, quic_shashim@quicinc.com, quic_kaushalk@quicinc.com, quic_tdas@quicinc.com, quic_tingweiz@quicinc.com, quic_aiquny@quicinc.com, kernel@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org References: <20241114095409.2682558-1-quic_ziyuzhan@quicinc.com> <20241114095409.2682558-5-quic_ziyuzhan@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: _oqmdhHv42GmmBFZH2D65SsX6y8eaaST X-Proofpoint-GUID: _oqmdhHv42GmmBFZH2D65SsX6y8eaaST X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 bulkscore=0 clxscore=1015 mlxlogscore=706 priorityscore=1501 phishscore=0 malwarescore=0 suspectscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411140102 On 14.11.2024 1:10 PM, Dmitry Baryshkov wrote: > On Thu, Nov 14, 2024 at 05:54:08PM +0800, Ziyue Zhang wrote: >> Add configurations in devicetree for PCIe0, including registers, clocks, >> interrupts and phy setting sequence. >> >> Signed-off-by: Ziyue Zhang >> --- >> arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 44 +++++- >> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 176 ++++++++++++++++++++++ >> 2 files changed, 219 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts >> index 7eed19a694c3..9d7c8555ed38 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts >> +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts >> @@ -213,7 +213,7 @@ vreg_l9c: ldo9 { >> &gcc { > > The patch doesn't seem to update the gcc node in qcs8300.dtsi. Is there > any reason to have the clocks property in the board data file? Definitely not. Ziyue, please move that change to the soc dtsi Konrad