Re: [PATCH 1/2] x86/PCI: Disable enhanced atomics on some AMD PCIe ports

[Mario Limonciello <mario.limonciello@amd.com>]

On 9/8/26 14:18, Bjorn Helgaas wrote:
> On Tue, Sep 08, 2026 at 12:00:34PM -0500, Mario Limonciello wrote:
>> There have been multiple reports of data corruption that can occur
>> with 64-bit DMA when the IOMMU is enabled. This occurs due to some
>> BIOSes enabling enhanced atomic operations on PCIe ports.
>>
>> When enhanced atomic operations are enabled on PCIe ports for some
>> models, data corruption occurs when the 32-bit IOVA space is exhausted.
>> The problem is reported on storage devices, but can affect any device
>> that uses 64 bit DMA.
> 
> I assume this means there's an erratum where NBIO doesn't handle
> 64-bit DMA correctly when some AMD-specific "enhanced atomics" are
> enabled?
> 
> Nothing to do with the atomic operations defined by the PCI specs?

Correct; nothing to do with atomic operations in PCI spec.

Note: I did post a v2 as Sashiko found a (valid) problem that this 
policy fixup needs to be applied during resume as well.

> 
>> Disable enhanced atomics using SMN for NBIO 7.7 and 7.11 based models.
>>
>> Cc: david.laight.linux@gmail.com
>> Cc: John Smith <imjohnsmith4000@gmail.com>
>> Cc: Lennert Buytenhek <kernel@wantstofly.org>
>> Cc: Niklas Cassel <cassel@kernel.org>
>> Cc: Roland Waltersson <roland.waltersson@netinsight.net>
>> Reported-by: Mikael Etienne <mikael1022bzh@gmail.com>
>> Closes: https://lore.kernel.org/all/178789300872.392066.15963676631650361573@gmail.com/
>> Reported-by: Arthur Husband <artmoty@gmail.com>
>> Closes: https://lore.kernel.org/linux-ide/20260406222335.379935-1-artmoty@gmail.com/
>> Reported-by: Alvin Lim <alvinwylim@gmail.com>
>> Closes: https://lore.kernel.org/linux-ide/20260621100844.1224301-1-alvinwylim@gmail.com/
>> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
>> ---
>>   arch/x86/pci/fixup.c | 93 ++++++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 93 insertions(+)
>>
>> diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
>> index b301c6c8df753..0857fd9365ec2 100644
>> --- a/arch/x86/pci/fixup.c
>> +++ b/arch/x86/pci/fixup.c
>> @@ -886,6 +886,99 @@ static void quirk_clear_strap_no_soft_reset_dev2_f0(struct pci_dev *dev)
>>   	}
>>   }
>>   DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b8, quirk_clear_strap_no_soft_reset_dev2_f0);
>> +
>> +/*
>> + * Enhanced atomic operations can cause corruption with 64-bit IOVA
>> + * on these devices.
>> + */
>> +#define RX_ENH_ATOMIC_EN		BIT(8)
>> +
>> +static const u32 nbio_7_7_pcie_smn_addrs[] = {
>> +	0x111401d0,
>> +	0x111411d0,
>> +	0x111421d0,
>> +	0x111431d0,
>> +	0x111441d0,
>> +	0x112401d0,
>> +	0x112411d0,
>> +	0x112421d0,
>> +	0x112431d0,
>> +	0x112441d0,
>> +	0x112451d0,
>> +	0x113401d0,
>> +	0x114401d0,
>> +};
>> +
>> +static const u32 nbio_7_11_pcie_smn_addrs[] = {
>> +	0x112401d0,
>> +	0x112411d0,
>> +	0x112421d0,
>> +	0x112431d0,
>> +	0x112441d0,
>> +	0x112451d0,
>> +	0x113401d0,
>> +	0x113411d0,
>> +	0x113421d0,
>> +	0x113431d0,
>> +	0x113441d0,
>> +	0x113451d0,
>> +};
>> +
>> +static void quirk_amd_nbio_enhanced_atomic(struct pci_dev *host_bridge,
>> +					   const u32 *smn_addrs,
>> +					   size_t nr_smn_addrs)
>> +{
>> +	bool changed = false;
>> +	size_t i;
>> +	u32 data;
>> +	int ret;
>> +
>> +	for (i = 0; i < nr_smn_addrs; i++) {
>> +		ret = amd_smn_read(0, smn_addrs[i], &data);
>> +		if (ret)
>> +			continue;
>> +		if (!(data & RX_ENH_ATOMIC_EN))
>> +			continue;
>> +		data = data & ~RX_ENH_ATOMIC_EN;
>> +		ret = amd_smn_write(0, smn_addrs[i], data);
>> +		if (ret)
>> +			continue;
>> +		if (changed)
>> +			continue;
>> +		ret = amd_smn_read(0, smn_addrs[i], &data);
>> +		if (ret)
>> +			continue;
>> +		if (data & RX_ENH_ATOMIC_EN)
>> +			continue;
>> +		changed = true;
>> +	}
>> +
>> +	if (changed)
>> +		pci_info(host_bridge, "enhanced atomics disabled\n");
>> +}
>> +
>> +static void quirk_amd_nbio_7_7_disable_enhanced_atomic(struct pci_dev *dev)
>> +{
>> +	quirk_amd_nbio_enhanced_atomic(dev, nbio_7_7_pcie_smn_addrs,
>> +				       ARRAY_SIZE(nbio_7_7_pcie_smn_addrs));
>> +}
>> +
>> +static void quirk_amd_nbio_7_11_disable_enhanced_atomic(struct pci_dev *dev)
>> +{
>> +	quirk_amd_nbio_enhanced_atomic(dev, nbio_7_11_pcie_smn_addrs,
>> +				       ARRAY_SIZE(nbio_7_11_pcie_smn_addrs));
>> +}
>> +
>> +/* Phoenix, Hawk Point (NBIO 7.7) */
>> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x14E8,
>> +			quirk_amd_nbio_7_7_disable_enhanced_atomic);
>> +
>> +/* Strix, Krackan, Strix Halo (NBIO 7.11) */
>> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1507,
>> +			quirk_amd_nbio_7_11_disable_enhanced_atomic);
>> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1122,
>> +			quirk_amd_nbio_7_11_disable_enhanced_atomic);
>> +
>>   #endif
>>   
>>   /*
>> -- 
>> 2.43.0
>>