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Mon, 08 Jun 2026 07:37:13 -0700 (PDT) X-Received: by 2002:a05:6a00:4c0a:b0:842:708f:39a6 with SMTP id d2e1a72fcca58-842b0e1e208mr15671413b3a.10.1780929433126; Mon, 08 Jun 2026 07:37:13 -0700 (PDT) Received: from [10.219.56.113] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84282221470sm19692216b3a.6.2026.06.08.07.37.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Jun 2026 07:37:12 -0700 (PDT) Message-ID: <26d51cbb-2d87-4564-b3c6-cc61ab900e19@oss.qualcomm.com> Date: Mon, 8 Jun 2026 20:07:07 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/6] arm64: dts: qcom: kodiak: Add GEM_NOC interconnect for adreno SMMU To: Dmitry Baryshkov Cc: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org References: <20260526-smmu_interconnect_addition-v2-0-2a6d8ca30d63@oss.qualcomm.com> <20260526-smmu_interconnect_addition-v2-3-2a6d8ca30d63@oss.qualcomm.com> Content-Language: en-US From: Bibek Kumar Patro In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA4MDEzOCBTYWx0ZWRfX7uIrkjB7HVaJ Vvbv2KusdFTwTvOfU3NIKq3aSS7IznykdFBtVZAEVCDYOmwOfPFSIkqsA9OqUFKo0wam2YmSaA1 tu+I9E4/9MKvl2qZvqxHcZcd07+d8OZyYAL/8BM/QkqMRHwGmbzrBuTijmGsGn/jOwbu7jC7rVt kH3aic+FBGMA5UsG3CZIoGLA4qG2gfIdl/jdxuELmjYJ7sIdC1sbwdtNa/yHwdWsN6Cd4iV2eAy qSHZ4KNyXUk6ZdIknqapGUjq4ldxnVGTCNZpUA+dHIKfu9C4esq1aW2YVZVeKbFa4HUsqSqbHdS Axs2RkchujgocTOx4v2l3Up/qgprsaaLAH7SwF0k3HT/jtyePc7lbbtEEkcQ9uRfhRNxVfeaMbA 6mUB+cDAH9tmkoRtABtl1SY91RiKQYyg/Nt22u96H8iWBXHY4XyES2E1OCU6LP1yQj2ZrceI6kt pgGyzFrs/lTcuNomSyw== X-Authority-Analysis: v=2.4 cv=V6BNF+ni c=1 sm=1 tr=0 ts=6a26d39a cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=5xEeDdGLKqE-Cjx_tAgA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-GUID: rZ8mjxzxX1pLDJDEi64_QQcKWNRYI2_v X-Proofpoint-ORIG-GUID: rZ8mjxzxX1pLDJDEi64_QQcKWNRYI2_v X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-08_04,2026-06-05_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 spamscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 bulkscore=0 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606080138 On 6/8/2026 7:27 PM, Dmitry Baryshkov wrote: > On Tue, May 26, 2026 at 08:12:04PM +0530, Bibek Kumar Patro wrote: >> On Kodiak platforms, the Adreno SMMU requires a bandwidth vote on >> the GEM_NOC path (MASTER_GPU_TCU -> SLAVE_EBI1) before its registers >> are accessible. Without this vote, the SMMU may become unreachable, >> leading to intermittent probe failures and runtime issues. >> >> Add the required interconnect to ensure reliable register access. > > Does it only concern the GPU SMMU? What about the APPS SMMU? Should it > be voting on other interconnects too? I guess so, because currently I > see that TBUs vote for various interconnects. BTW: should apps_smmu also > vote on the power domains? > This race mainly occurs in GPU SMMU, where the GDSC can have an independent vote on the Adreno SMMU. However, the GEM_NOC vote may already have been removed by the GPU (or any consumer of adreno_smmu, e.g gmu), unless it is explicitly voted by the GPU SMMU (which acts as a supplier for the GPU). This mismatch can lead to SHUB timeouts or NoC errors. Mostly this race reported in suspend/resume cycle (when gpu/gmu devices moves to slumber/suspend state before adreno_smmu powers down and the later doesn't have explicit interconnect voting). In the case of APPS SMMU, such a race is not expected for any known use case. APPS SMMU is part of a shared infrastructure block, and its power is typically kept enabled as long as attached master devices are active. Therefore, explicit power-domain voting from APPS SMMU may not be required. Thanks, Bibek >> >> Signed-off-by: Bibek Kumar Patro >> --- >> arch/arm64/boot/dts/qcom/kodiak.dtsi | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi >> index fa540d8c2615dc02d941eb16bc7253204c2750bd..eefa4b836a81374ff437ab4bbcbc3fecc1590ab6 100644 >> --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi >> +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi >> @@ -3386,6 +3386,8 @@ adreno_smmu: iommu@3da0000 { >> >> power-domains = <&gpucc GPU_CC_CX_GDSC>; >> dma-coherent; >> + interconnects = <&gem_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> }; >> >> gfx_0_tbu: tbu@3dd9000 { >> >> -- >> 2.34.1 >> >