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[83.9.32.99]) by smtp.gmail.com with ESMTPSA id q8-20020ac246e8000000b004b6efcb7bb5sm1651026lfo.169.2023.03.06.06.04.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Mar 2023 06:04:18 -0800 (PST) Message-ID: <27109715-ffda-2a4a-ee67-886713103d49@linaro.org> Date: Mon, 6 Mar 2023 15:04:16 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH RFT 03/20] clk: qcom: smd-rpm: Add support for keepalive votes Content-Language: en-US From: Konrad Dybcio To: Dmitry Baryshkov Cc: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo , Taniya Das References: <20230303-topic-rpmcc_sleep-v1-0-d9cfaf9b27a7@linaro.org> <20230303-topic-rpmcc_sleep-v1-3-d9cfaf9b27a7@linaro.org> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 6.03.2023 12:28, Konrad Dybcio wrote: > > > On 6.03.2023 02:21, Dmitry Baryshkov wrote: >> On Sat, 4 Mar 2023 at 15:27, Konrad Dybcio wrote: >>> >>> Some bus clock should always have a minimum (19.2 MHz) vote cast on >>> them, otherwise the platform will fall apart, hang and reboot. >>> >>> Add support for specifying which clocks should be kept alive and >>> always keep a vote on XO_A to make sure the clock tree doesn't >>> collapse. This removes the need to keep a maximum vote that was >>> previously guaranteed by clk_smd_rpm_handoff. >>> >>> This commit is a combination of existing (not-exactly-upstream) work >>> by Taniya Das, Shawn Guo and myself. >>> >>> Co-developed-by: Shawn Guo >>> Co-developed-by: Taniya Das >>> Signed-off-by: Konrad Dybcio >>> --- [...] >> >>> + >>> + ret = clk_set_rate(keepalive_clks[i]->clk, 19200000); >> >> Don't we also need to provide a determine_rate() that will not allow >> one to set clock frequency below 19.2 MHz? > Hm, sounds like a good idea.. Thinking about it again, I'd have to do it before the clocks are registered and we'd either end up with 2 loops, one assigning the CLK_IS_CRITICAL flag and the other one setting the rate.. Will that not be too hacky? Konrad > >> >>> + if (ret) >>> + return ret; >>> + } >>> + >>> + /* Keep an active vote on CXO in case no other driver votes for it. */ >>> + if (rpm_smd_clks[RPM_SMD_XO_A_CLK_SRC]) >>> + return clk_prepare_enable(rpm_smd_clks[RPM_SMD_XO_A_CLK_SRC]->hw.clk); >>> + >>> return 0; >>> err: >>> dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret); >> >> >> I have mixed feelings towards this patch (and the rest of the >> patchset). It looks to me like we are trying to patch an issue of the >> interconnect drivers (or in kernel configuration). > Well, as you noticed, this patch tries to address a situation where a > critical clock could be disabled. The interconnect driver (as per my > other recent patchset) also has a concept of "keepalive", but: > > 1. not very many SoCs already have a functional icc driver > 2. devices with an existing interconnect driver should also be > testable without one (through painful ripping out everything-icc > from the dts) for regression tracking > > Konrad > >> >> >> -- >> With best wishes >> Dmitry