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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2466889f11esm116975865ad.150.2025.08.27.02.18.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Aug 2025 02:18:43 -0700 (PDT) Message-ID: <27282f8d-e27d-45c9-b616-28d2c62a4e09@oss.qualcomm.com> Date: Wed, 27 Aug 2025 17:18:37 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] coresight: tpda: add sysfs nodes for tpda cross-trigger configuration To: James Clark Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Suzuki K Poulose , Mike Leach , Alexander Shishkin , Tingwei Zhang References: <20250827042042.6786-1-jie.gan@oss.qualcomm.com> <20250827042042.6786-2-jie.gan@oss.qualcomm.com> <5acf3562-e69a-49b0-8cb6-9e57c5ad4368@linaro.org> Content-Language: en-US From: Jie Gan In-Reply-To: <5acf3562-e69a-49b0-8cb6-9e57c5ad4368@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=cLDgskeN c=1 sm=1 tr=0 ts=68aecd75 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=OiUlF2ysgpT-6eO3SmwA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODI2MDE1MyBTYWx0ZWRfX6E/qokIAkyXi EOP1dkPCNXBqUr2K2bWSXw2HHATbfpOyKCvMc6Oip2PFMAT0OSooBwPn0rojHTcezmW/4hygzzd 72A914/LzPLI4DiRGYhd3vFCAZtOTAXHMf7B8htQL66LpgKdPR3PDJ4R01d/2pTl0931Ori7nAT ucChyDuho6iebCOES2XyZid/IE6mPrh6UMZkLPEzARRQVR+r8jaVocSgVw5Qthq2scscImy8LQE l+UJzIIR0pfpquGreBrd6XrTJeNnWN0suQL425kH6EW/zeTxFuG3jWa1PFfq5aa5911bH/YJcx7 W8qGTNEpxXp3j4CkieoeipAlTmzSfDRoYHpaewTZbM4UjxdB2qOwWL4gXiUQwsR8SHEsAyKS/Ta XQ0RtPXO X-Proofpoint-GUID: HNzjWCyTdmoZZ-dsMLipEd2nmLpSRLzR X-Proofpoint-ORIG-GUID: HNzjWCyTdmoZZ-dsMLipEd2nmLpSRLzR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-27_01,2025-08-26_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 malwarescore=0 spamscore=0 adultscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508260153 On 8/27/2025 5:06 PM, James Clark wrote: > > > On 27/08/2025 5:20 am, Jie Gan wrote: >> From: Tao Zhang >> >> Introduce sysfs nodes to configure cross-trigger parameters for TPDA. >> These registers define the characteristics of cross-trigger packets, >> including generation frequency and flag values. >> >> Signed-off-by: Tao Zhang >> Co-developed-by: Jie Gan >> Signed-off-by: Jie Gan >> --- >>   .../testing/sysfs-bus-coresight-devices-tpda  |  43 ++++ >>   drivers/hwtracing/coresight/coresight-tpda.c  | 227 ++++++++++++++++++ >>   drivers/hwtracing/coresight/coresight-tpda.h  |  27 ++- >>   3 files changed, 296 insertions(+), 1 deletion(-) >>   create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight- >> devices-tpda >> >> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices- >> tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >> new file mode 100644 >> index 000000000000..fb651aebeb31 >> --- /dev/null >> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda >> @@ -0,0 +1,43 @@ >> +What:        /sys/bus/coresight/devices//trig_async_enable >> +Date:        August 2025 >> +KernelVersion:    6.17 >> +Contact:    Jinlong Mao , Tao Zhang >> , Jie Gan >> +Description: >> +        (RW) Enable/disable cross trigger synchronization sequence >> interface. >> + >> +What:        /sys/bus/coresight/devices//trig_flag_ts_enable >> +Date:        August 2025 >> +KernelVersion:    6.17 >> +Contact:    Jinlong Mao , Tao Zhang >> , Jie Gan >> +Description: >> +        (RW) Enable/disable cross trigger FLAG packet request interface. >> + >> +What:        /sys/bus/coresight/devices//trig_freq_enable >> +Date:        August 2025 >> +KernelVersion:    6.17 >> +Contact:    Jinlong Mao , Tao Zhang >> , Jie Gan >> +Description: >> +        (RW) Enable/disable cross trigger FREQ packet request interface. >> + >> +What:        /sys/bus/coresight/devices//freq_ts_enable >> +Date:        August 2025 >> +KernelVersion:    6.17 >> +Contact:    Jinlong Mao , Tao Zhang >> , Jie Gan >> +Description: >> +        (RW) Enable/disable the timestamp for all FREQ packets. >> + >> +What:        /sys/bus/coresight/devices//global_flush_req >> +Date:        August 2025 >> +KernelVersion:    6.17 >> +Contact:    Jinlong Mao , Tao Zhang >> , Jie Gan >> +Description: >> +        (RW) Set global (all ports) flush request bit. The bit >> remains set until a >> +        global flush request sequence completes. >> + >> +What:        /sys/bus/coresight/devices//cmbchan_mode >> +Date:        August 2025 >> +KernelVersion:    6.17 >> +Contact:    Jinlong Mao , Tao Zhang >> , Jie Gan >> +Description: >> +        (RW) Configure the CMB/MCMB channel mode for all enabled ports. >> +        Value 0 means raw channel mapping mode. Value 1 means channel >> pair marking mode. >> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/ >> hwtracing/coresight/coresight-tpda.c >> index 4e93fa5bace4..647ab49a98d7 100644 >> --- a/drivers/hwtracing/coresight/coresight-tpda.c >> +++ b/drivers/hwtracing/coresight/coresight-tpda.c >> @@ -156,9 +156,37 @@ static void tpda_enable_pre_port(struct >> tpda_drvdata *drvdata) >>       u32 val; >>       val = readl_relaxed(drvdata->base + TPDA_CR); >> +    val &= ~TPDA_CR_MID; >>       val &= ~TPDA_CR_ATID; >>       val |= FIELD_PREP(TPDA_CR_ATID, drvdata->atid); >> +    if (drvdata->trig_async) >> +        val |= TPDA_CR_SRIE; >> +    else >> +        val &= ~TPDA_CR_SRIE; >> +    if (drvdata->trig_flag_ts) >> +        val |= TPDA_CR_FLRIE; >> +    else >> +        val &= ~TPDA_CR_FLRIE; >> +    if (drvdata->trig_freq) >> +        val |= TPDA_CR_FRIE; >> +    else >> +        val &= ~TPDA_CR_FRIE; >> +    if (drvdata->freq_ts) >> +        val |= TPDA_CR_FREQTS; >> +    else >> +        val &= ~TPDA_CR_FREQTS; >> +    if (drvdata->cmbchan_mode) >> +        val |= TPDA_CR_CMBCHANMODE; >> +    else >> +        val &= ~TPDA_CR_CMBCHANMODE; >>       writel_relaxed(val, drvdata->base + TPDA_CR); >> + >> +    /* >> +     * If FLRIE bit is set, set the master and channel >> +     * id as zero >> +     */ >> +    if (drvdata->trig_flag_ts) >> +        writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); >>   } >>   static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) >> @@ -274,6 +302,203 @@ static const struct coresight_ops tpda_cs_ops = { >>       .link_ops    = &tpda_link_ops, >>   }; >> +static ssize_t trig_async_enable_show(struct device *dev, >> +                      struct device_attribute *attr, >> +                      char *buf) >> +{ >> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> + >> +    return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_async); >> +} >> + >> +static ssize_t trig_async_enable_store(struct device *dev, >> +                       struct device_attribute *attr, >> +                       const char *buf, >> +                       size_t size) >> +{ >> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> +    unsigned long val; >> + >> +    if (kstrtoul(buf, 0, &val)) >> +        return -EINVAL; >> + >> +    guard(spinlock)(&drvdata->spinlock); >> +    drvdata->trig_async = !!val; >> + >> +    return size; >> +} >> +static DEVICE_ATTR_RW(trig_async_enable); >> + >> +static ssize_t trig_flag_ts_enable_show(struct device *dev, >> +                    struct device_attribute *attr, >> +                    char *buf) >> +{ >> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> + >> +    return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_flag_ts); >> +} >> + >> +static ssize_t trig_flag_ts_enable_store(struct device *dev, >> +                     struct device_attribute *attr, >> +                     const char *buf, >> +                     size_t size) >> +{ >> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> +    unsigned long val; >> + >> +    if (kstrtoul(buf, 0, &val)) >> +        return -EINVAL; >> + >> +    guard(spinlock)(&drvdata->spinlock); >> +    drvdata->trig_flag_ts = !!val; >> + >> +    return size; >> +} >> +static DEVICE_ATTR_RW(trig_flag_ts_enable); >> + >> +static ssize_t trig_freq_enable_show(struct device *dev, >> +                     struct device_attribute *attr, >> +                     char *buf) >> +{ >> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> + >> +    return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_freq); >> +} >> + >> +static ssize_t trig_freq_enable_store(struct device *dev, >> +                      struct device_attribute *attr, >> +                      const char *buf, >> +                      size_t size) >> +{ >> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> +    unsigned long val; >> + >> +    if (kstrtoul(buf, 0, &val)) >> +        return -EINVAL; >> + >> +    guard(spinlock)(&drvdata->spinlock); >> +    drvdata->trig_freq = !!val; >> + >> +    return size; >> +} >> +static DEVICE_ATTR_RW(trig_freq_enable); >> + >> +static ssize_t freq_ts_enable_show(struct device *dev, >> +                   struct device_attribute *attr, >> +                   char *buf) >> +{ >> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> + >> +    return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->freq_ts); >> +} >> + >> +static ssize_t freq_ts_enable_store(struct device *dev, >> +                    struct device_attribute *attr, >> +                    const char *buf, >> +                    size_t size) >> +{ >> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> +    unsigned long val; >> + >> +    if (kstrtoul(buf, 0, &val)) >> +        return -EINVAL; >> + >> +    guard(spinlock)(&drvdata->spinlock); >> +    drvdata->freq_ts = !!val; >> + >> +    return size; >> +} >> +static DEVICE_ATTR_RW(freq_ts_enable); >> + >> +static ssize_t global_flush_req_show(struct device *dev, >> +                     struct device_attribute *attr, >> +                     char *buf) >> +{ >> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> +    unsigned long val; >> + >> +    if (!drvdata->csdev->refcnt) >> +        return -EINVAL; >> + >> +    guard(spinlock)(&drvdata->spinlock); >> +    CS_UNLOCK(drvdata->base); >> +    val = readl_relaxed(drvdata->base + TPDA_CR); >> +    CS_LOCK(drvdata->base); >> + >> +    return sysfs_emit(buf, "%lx\n", val); > > I know in practice it's probably only either 0 or 1, but this should > either be decimal or have the 0x prefix otherwise it looks like a mistake. > You are right. It looks strange here and I missed this point. I think display the value in decimal would be better. >> +} >> + >> +static ssize_t global_flush_req_store(struct device *dev, >> +                      struct device_attribute *attr, >> +                      const char *buf, >> +                      size_t size) >> +{ >> +    struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); >> +    unsigned long val; >> + >> +    if (kstrtoul(buf, 0, &val)) >> +        return -EINVAL; >> + >> +    if (!drvdata->csdev->refcnt || !val) >> +        return -EINVAL; >> + >> +    guard(spinlock)(&drvdata->spinlock); >> +    CS_UNLOCK(drvdata->base); >> +    val = readl_relaxed(drvdata->base + TPDA_CR); >> +    val |= BIT(0); > > If you only set bit 0 do you only want to show bit 0 in > global_flush_req_show() above? The sysfs files should be divided up by > function rather than dumping the whole register, otherwise tools need > their own copy of the fields to interperet them. Got your point here. In the show function, we only need read the value of the bit 0 and display the value. Thanks, Jie > >