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b=ZmveOCcm8ZcsmHRIllBgO98a/vVnUzkIsozqtPaXzq3AJ4oEcOMkLmjecm4BcyYRD9mAyTury0wSvbpx4FHjhko0LxKxXO1iDwfeAPprnzn73pBa9Yfc0EtIwVQfKTksNJ2TuoyHrW6/IrtUSDFC8WgTmQagrD9G9UUiNFeq8iY= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from PH7PR12MB6588.namprd12.prod.outlook.com (2603:10b6:510:210::10) by IA0PR12MB8840.namprd12.prod.outlook.com (2603:10b6:208:490::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8182.14; Tue, 19 Nov 2024 13:36:57 +0000 Received: from PH7PR12MB6588.namprd12.prod.outlook.com ([fe80::5e9c:4117:b5e0:cf39]) by PH7PR12MB6588.namprd12.prod.outlook.com ([fe80::5e9c:4117:b5e0:cf39%4]) with mapi id 15.20.8158.019; Tue, 19 Nov 2024 13:36:57 +0000 Message-ID: <2743666a-f592-4ee2-af43-757c6d8ca64c@amd.com> Date: Tue, 19 Nov 2024 19:06:45 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] perf/amd/ibs: Add support for OP Load Latency Filtering To: peterz@infradead.org, mingo@redhat.com, namhyung@kernel.org Cc: acme@kernel.org, eranian@google.com, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, tglx@linutronix.de, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, santosh.shukla@amd.com, ananth.narayan@amd.com, sandipan.das@amd.com References: <20241010050815.751-1-ravi.bangoria@amd.com> Content-Language: en-US From: Ravi Bangoria In-Reply-To: <20241010050815.751-1-ravi.bangoria@amd.com> Content-Type: text/plain; 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It's advertised by CPUID_Fn8000001B_EAX bit 12. > When enabled, IBS hw will raise interrupts only for samples that had > an IbsDcMissLat value greater than N cycles, where N is a programmable > value defined as multiples of 128 (i.e., 128, 256, 512 etc.) from > 128-2048 cycles. L3MissOnly is a mandatory dependency for LdLat, and > like L3MissOnly, Hardware internally drops the sample and restarts if > the sample does not meet the filtering condition. > > Add support for LdLat filtering in IBS Op pmu. Since hardware supports > threshold in multiple of 128, add a software filter on top to support > latency threshold with the granularity of 1 cycle between [128-2048]. > > Example usage: > # perf record -a -e ibs_op/l3missonly=1,ldlat=128/ -- sleep 5 > > Signed-off-by: Ravi Bangoria > --- > > Note: IBS sample period cleanup patches are pre-req for this. > https://lore.kernel.org/r/20241007034810.754-1-ravi.bangoria@amd.com Peter/Ingo, gentle reminder. Thanks, Ravi