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AJvYcCXqv2cTfaPmA3FU2jk4aQD/CCOB0xyKhjYhrP30LOOESfyI46riEkNhwajK40DrHdTsoJFVqgVc4heCyoc=@vger.kernel.org X-Gm-Message-State: AOJu0YyLpycZc+nQX9Xf6G/Cfpr1c7Sqx0g/j5eh02l0rgqcj8i3WVhA d9acQIIL2E42yV4xF913k5KNGHobGH+9Gtejn3dMPTY4jZ9wZ5RQ4+narwiSLng= X-Google-Smtp-Source: AGHT+IFhlE6ZrY41rmkc+9XGmW+fZeuwq4JG6dHsE1M5Fq87WTjwrS/Nh6wLsDQBUZUkcgmyZ7UGWg== X-Received: by 2002:a5d:5192:0:b0:374:c9f0:752d with SMTP id ffacd0b85a97d-378896a5ca3mr1851961f8f.47.1725638010354; Fri, 06 Sep 2024 08:53:30 -0700 (PDT) Received: from [192.168.0.20] ([148.56.230.39]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42ca05cfb47sm24222555e9.22.2024.09.06.08.53.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Sep 2024 08:53:30 -0700 (PDT) Message-ID: <276a7f04-6761-40c2-8f37-799175f9b11b@suse.com> Date: Fri, 6 Sep 2024 17:53:28 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] arm64: dts: s32g: Add S32G2/S32G3 uSDHC pinmux To: Ciprian Costea , Chester Lin , Ghennadi Procopciuc , Shawn Guo , Sascha Hauer , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Pengutronix Kernel Team , linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, NXP S32 Linux Team , Radu Pirea References: <20240830113347.4048370-1-ciprianmarian.costea@oss.nxp.com> <20240830113347.4048370-2-ciprianmarian.costea@oss.nxp.com> Content-Language: en-US, ca-ES, es-ES From: Matthias Brugger Autocrypt: addr=mbrugger@suse.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 30/08/2024 13:33, Ciprian Costea wrote: > From: Ciprian Marian Costea > > Adding 100mhz & 200mhz pinmux support for uSDHC helps to enable > higher speed modes for SD (SDR50, DDR50, SDR104) and > eMMC (such as HS200, HS400/HS400ES). > > Signed-off-by: Radu Pirea > Signed-off-by: Ciprian Marian Costea Reviewed-by: Matthias Brugger > --- > arch/arm64/boot/dts/freescale/s32g2.dtsi | 153 ++++++++++++++++++ > .../arm64/boot/dts/freescale/s32g274a-evb.dts | 4 + > .../boot/dts/freescale/s32g274a-rdb2.dts | 4 + > arch/arm64/boot/dts/freescale/s32g3.dtsi | 153 ++++++++++++++++++ > .../boot/dts/freescale/s32g399a-rdb3.dts | 4 + > 5 files changed, 318 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi > index fa054bfe7d5c..7be430b78c83 100644 > --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi > @@ -162,6 +162,159 @@ jtag-grp4 { > slew-rate = <166>; > }; > }; > + > + pinctrl_usdhc0: usdhc0grp-pins { > + usdhc0-grp0 { > + pinmux = <0x2e1>, > + <0x381>; > + output-enable; > + bias-pull-down; > + slew-rate = <150>; > + }; > + > + usdhc0-grp1 { > + pinmux = <0x2f1>, > + <0x301>, > + <0x311>, > + <0x321>, > + <0x331>, > + <0x341>, > + <0x351>, > + <0x361>, > + <0x371>; > + output-enable; > + input-enable; > + bias-pull-up; > + slew-rate = <150>; > + }; > + > + usdhc0-grp2 { > + pinmux = <0x391>; > + output-enable; > + slew-rate = <150>; > + }; > + > + usdhc0-grp3 { > + pinmux = <0x3a0>; > + input-enable; > + slew-rate = <150>; > + }; > + > + usdhc0-grp4 { > + pinmux = <0x2032>, > + <0x2042>, > + <0x2052>, > + <0x2062>, > + <0x2072>, > + <0x2082>, > + <0x2092>, > + <0x20a2>, > + <0x20b2>, > + <0x20c2>; > + }; > + }; > + > + pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins { > + usdhc0-100mhz-grp0 { > + pinmux = <0x2e1>, > + <0x381>; > + output-enable; > + bias-pull-down; > + slew-rate = <150>; > + }; > + > + usdhc0-100mhz-grp1 { > + pinmux = <0x2f1>, > + <0x301>, > + <0x311>, > + <0x321>, > + <0x331>, > + <0x341>, > + <0x351>, > + <0x361>, > + <0x371>; > + output-enable; > + input-enable; > + bias-pull-up; > + slew-rate = <150>; > + }; > + > + usdhc0-100mhz-grp2 { > + pinmux = <0x391>; > + output-enable; > + slew-rate = <150>; > + }; > + > + usdhc0-100mhz-grp3 { > + pinmux = <0x3a0>; > + input-enable; > + slew-rate = <150>; > + }; > + > + usdhc0-100mhz-grp4 { > + pinmux = <0x2032>, > + <0x2042>, > + <0x2052>, > + <0x2062>, > + <0x2072>, > + <0x2082>, > + <0x2092>, > + <0x20a2>, > + <0x20b2>, > + <0x20c2>; > + }; > + }; > + > + pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins { > + usdhc0-200mhz-grp0 { > + pinmux = <0x2e1>, > + <0x381>; > + output-enable; > + bias-pull-down; > + slew-rate = <208>; > + }; > + > + usdhc0-200mhz-grp1 { > + pinmux = <0x2f1>, > + <0x301>, > + <0x311>, > + <0x321>, > + <0x331>, > + <0x341>, > + <0x351>, > + <0x361>, > + <0x371>; > + output-enable; > + input-enable; > + bias-pull-up; > + slew-rate = <208>; > + }; > + > + usdhc0-200mhz-grp2 { > + pinmux = <0x391>; > + output-enable; > + slew-rate = <208>; > + }; > + > + usdhc0-200mhz-grp3 { > + pinmux = <0x3a0>; > + input-enable; > + slew-rate = <208>; > + }; > + > + usdhc0-200mhz-grp4 { > + pinmux = <0x2032>, > + <0x2042>, > + <0x2052>, > + <0x2062>, > + <0x2072>, > + <0x2082>, > + <0x2092>, > + <0x20a2>, > + <0x20b2>, > + <0x20c2>; > + }; > + }; > }; > > uart0: serial@401c8000 { > diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts > index dbe498798bd9..7ab917f547ef 100644 > --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts > +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts > @@ -34,6 +34,10 @@ &uart0 { > }; > > &usdhc0 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc0>; > + pinctrl-1 = <&pinctrl_usdhc0_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc0_200mhz>; > disable-wp; > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts > index ab1e5caaeae7..8739f63771bc 100644 > --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts > +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts > @@ -40,6 +40,10 @@ &uart1 { > }; > > &usdhc0 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc0>; > + pinctrl-1 = <&pinctrl_usdhc0_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc0_200mhz>; > disable-wp; > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi > index b4226a9143c8..6c572ffe37ca 100644 > --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi > +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi > @@ -219,6 +219,159 @@ jtag-grp4 { > slew-rate = <166>; > }; > }; > + > + pinctrl_usdhc0: usdhc0grp-pins { > + usdhc0-grp0 { > + pinmux = <0x2e1>, > + <0x381>; > + output-enable; > + bias-pull-down; > + slew-rate = <150>; > + }; > + > + usdhc0-grp1 { > + pinmux = <0x2f1>, > + <0x301>, > + <0x311>, > + <0x321>, > + <0x331>, > + <0x341>, > + <0x351>, > + <0x361>, > + <0x371>; > + output-enable; > + input-enable; > + bias-pull-up; > + slew-rate = <150>; > + }; > + > + usdhc0-grp2 { > + pinmux = <0x391>; > + output-enable; > + slew-rate = <150>; > + }; > + > + usdhc0-grp3 { > + pinmux = <0x3a0>; > + input-enable; > + slew-rate = <150>; > + }; > + > + usdhc0-grp4 { > + pinmux = <0x2032>, > + <0x2042>, > + <0x2052>, > + <0x2062>, > + <0x2072>, > + <0x2082>, > + <0x2092>, > + <0x20a2>, > + <0x20b2>, > + <0x20c2>; > + }; > + }; > + > + pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins { > + usdhc0-100mhz-grp0 { > + pinmux = <0x2e1>, > + <0x381>; > + output-enable; > + bias-pull-down; > + slew-rate = <150>; > + }; > + > + usdhc0-100mhz-grp1 { > + pinmux = <0x2f1>, > + <0x301>, > + <0x311>, > + <0x321>, > + <0x331>, > + <0x341>, > + <0x351>, > + <0x361>, > + <0x371>; > + output-enable; > + input-enable; > + bias-pull-up; > + slew-rate = <150>; > + }; > + > + usdhc0-100mhz-grp2 { > + pinmux = <0x391>; > + output-enable; > + slew-rate = <150>; > + }; > + > + usdhc0-100mhz-grp3 { > + pinmux = <0x3a0>; > + input-enable; > + slew-rate = <150>; > + }; > + > + usdhc0-100mhz-grp4 { > + pinmux = <0x2032>, > + <0x2042>, > + <0x2052>, > + <0x2062>, > + <0x2072>, > + <0x2082>, > + <0x2092>, > + <0x20a2>, > + <0x20b2>, > + <0x20c2>; > + }; > + }; > + > + pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins { > + usdhc0-200mhz-grp0 { > + pinmux = <0x2e1>, > + <0x381>; > + output-enable; > + bias-pull-down; > + slew-rate = <208>; > + }; > + > + usdhc0-200mhz-grp1 { > + pinmux = <0x2f1>, > + <0x301>, > + <0x311>, > + <0x321>, > + <0x331>, > + <0x341>, > + <0x351>, > + <0x361>, > + <0x371>; > + output-enable; > + input-enable; > + bias-pull-up; > + slew-rate = <208>; > + }; > + > + usdhc0-200mhz-grp2 { > + pinmux = <0x391>; > + output-enable; > + slew-rate = <208>; > + }; > + > + usdhc0-200mhz-grp3 { > + pinmux = <0x3a0>; > + input-enable; > + slew-rate = <208>; > + }; > + > + usdhc0-200mhz-grp4 { > + pinmux = <0x2032>, > + <0x2042>, > + <0x2052>, > + <0x2062>, > + <0x2072>, > + <0x2082>, > + <0x2092>, > + <0x20a2>, > + <0x20b2>, > + <0x20c2>; > + }; > + }; > }; > > uart0: serial@401c8000 { > diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts > index 176e5af191c8..828e353455b5 100644 > --- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts > +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts > @@ -40,6 +40,10 @@ &uart1 { > }; > > &usdhc0 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc0>; > + pinctrl-1 = <&pinctrl_usdhc0_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc0_200mhz>; > bus-width = <8>; > disable-wp; > status = "okay";