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Mon, 02 Nov 2026 22:12:05 -0800 (PST) Received: from ehlo.thunderbird.net ([168.138.199.194]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b07c627260sm2564063a91.8.2026.11.02.22.12.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Nov 2026 22:12:04 -0800 (PST) Date: Tue, 03 Nov 2026 14:11:59 +0800 From: Coia Prant To: Andrew Lunn CC: Maxime Chevallier , Jakub Kicinski , Heiner Kallweit , Russell King , "David S . Miller" , Eric Dumazet , Paolo Abeni , netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH net] net: pcs: xpcs-rk: limit advertised interfaces User-Agent: K-9 Mail for Android In-Reply-To: <48cb8a9d-622f-497c-a13e-bc679c764ce0@lunn.ch> References: <20261029094916.3127193-2-coiaprant@gmail.com> <1B8D463D-1295-4BF0-972D-859C342E49F5@gmail.com> <48cb8a9d-622f-497c-a13e-bc679c764ce0@lunn.ch> Message-ID: <27E466B0-72FD-47BA-B952-68BF4A817A04@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On November 3, 2026 10:54:57 AM GMT+08:00, Andrew Lunn w= rote: >> Hi Maxime, >>=20 >> You're right that for modes the PCS does implement, the limit belongs >> on the MAC side=2E The complication is that the compat table describes >> the whole Synopsys IP set, while a given XPCS instance only implements >> a subset of it=2E That is a historical design issue in pcs-xpcs: the >> table mixes C73, C37, 2500BASE-X and 10GBASE-X entries, but different >> integrations implement different subsets=2E >>=20 >> On RK3568 the XPCS instance is wired up for the C37 SGMII path only=2E >> 1000BASE-X is part of the same C37 core, but I don't have a PHY to test >> it against=2E QSGMII is not implemented in this core=2E 2500BASE-X and >> 10GBASE-X are separate modes the shared table carries, and neither is >> implemented on this SoC=2E C73 is not wired up either=2E >>=20 >> Trimming the mask is not limiting the PCS, it is cutting the shared >> table down to what this instance actually implements=2E A >> platform-specific glue is the right place to do that=2E > >Are there any registers which describe how the PCS was configured at >syntheses time? > > Andrew Hi Andrew, Yes, looking at the `xpcs_identity` code, the core does probe different MMDs to get the rough type: PMA/PMD MMD for C73 and VEND2 MMD for C37=2E However, even if we determine it's a C37 or C73 block, that only gives us the rough family, not the exact feature set=2E For example, a VEND2 (C37) block might not implement 2500BASE-X, and a PMA/PMD (C73) block might not implement 10GBASE-R=2E The MMD ID itself doesn't tell us which of these sub-modes were actually synthesized and wired out=2E Since I only have the Rockchip RK3568 PCS documentation, I don't want to blindly touch the global compat[] table in the core, as it could easily break other platforms (Intel, NXP, etc=2E)=2E That's why intersecting the platform mask with the core mask in the Rockchip glue is the safest approach for now=2E As a bit of context on where this is heading: currently, the PMA layers for wx, fbnic, and nxp are separate source files but are compiled into the generic core module, relying on a shared compat table=2E In a follow-up net-next series, I plan to split them into actual independent modules using an abstraction layer and their own xpcs_xxx_create() functions=2E This will allow other platforms (including Rockchip) to do the same mask intersection and PMA-specific setup without bloating the generic core with more and more platform quirks=2E Right now, dwmac-intel seems to be the only platform that completely relies on the generic core without a specific PMA module=2E So keeping the core generic and doing the narrowing in the glue is a safe, self-contained step that aligns with that future direction=2E Coia