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Thu, 30 Oct 2025 10:10:20 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHpVyI3SYzlsHFGKlaP/DnDt5s7dOcaIyHFJw2iqv5mOfOnAsbhrxBDiNQMBB+iz3GHGEeXLA== X-Received: by 2002:a05:6a00:99f:b0:774:1be4:dced with SMTP id d2e1a72fcca58-7a777576df1mr127063b3a.9.1761844220021; Thu, 30 Oct 2025 10:10:20 -0700 (PDT) Received: from [192.168.0.195] ([49.204.28.130]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7a445156004sm10128574b3a.51.2025.10.30.10.10.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 30 Oct 2025 10:10:19 -0700 (PDT) Message-ID: <27a1ba7c-6e72-4c86-8eed-bff9ab6f0c0c@oss.qualcomm.com> Date: Thu, 30 Oct 2025 22:40:15 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts To: Dmitry Baryshkov Cc: Konrad Dybcio , Pankaj Patil , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250925-v3_glymur_introduction-v1-0-24b601bbecc0@oss.qualcomm.com> <20250925-v3_glymur_introduction-v1-3-24b601bbecc0@oss.qualcomm.com> <2960a6fc-106b-4280-b4d4-9c1a3a449454@oss.qualcomm.com> <0a47016c-1d7e-4026-92bb-a13ac2ce169b@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDMwMDE0MSBTYWx0ZWRfX3aCUhy2g/y9D JZfncktQsU3UBUuf4WxTLBjpdWyJLiQz/W6pkLp8F8JRFA3dvvTLb6kak5sz8nR7ckYRHnL0U9y UVIe/Ct7MfChYQLKpFA/UetJXhZoinDsaUxEXh3AO5e6d6sV4aUQl15h4Er42otAUCoYbzakcL8 mr3kXLeq7QvXLO6hhDsztSAcNcy1PhyxdQCnNmnFIvSKoMKv33zOFNAjWissSEqaRZQNYo/GW/D MeXgbd4oHiXlGt1OQdF/PqS1fSgTLl6mhou7eQcp98S1W78+XqUqkAkYAjTgCFKx681Xh6PTpxo hSjFDVdP/BRu5noO8yOdtiqc7v34nfUS+o/ExivZl3jsjgPO+P9QhXNmqJI+4ogpN22/ihvEuiQ WPgtYotvLT7urfTFNg/5VskB7IWgMQ== X-Authority-Analysis: v=2.4 cv=P+Y3RyAu c=1 sm=1 tr=0 ts=69039bfd cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=kYOnW6kYNC4MuwyOue8uGA==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=RH4B9Nl3qsRc-XDkDe0A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-ORIG-GUID: f5wDk5KgGQEk1bzzHfLrIMzRurbC3qkC X-Proofpoint-GUID: f5wDk5KgGQEk1bzzHfLrIMzRurbC3qkC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-10-30_05,2025-10-29_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 malwarescore=0 adultscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2510300141 On 10/30/2025 4:39 PM, Dmitry Baryshkov wrote: > On Thu, 30 Oct 2025 at 12:44, Taniya Das wrote: >> >> >> >> On 10/29/2025 4:06 PM, Dmitry Baryshkov wrote: >>> On Wed, Oct 29, 2025 at 03:30:54PM +0530, Taniya Das wrote: >>>> >>>> >>>> On 9/25/2025 3:46 PM, Konrad Dybcio wrote: >>>>>> + tcsrcc: clock-controller@1fd5044 { >>>>>> + compatible = "qcom,glymur-tcsr"; >>>>>> + reg = <0x0 0x1fd5044 0x0 0x48>; >>>>> We can map 0x1fd5000 - 0x1fd5094 inclusive, as that seems like a >>>>> logical subblock (this would require adjusting the driver) >>>>> >>>> >>>> Konrad, we encountered issues when trying to map regions beyond just the >>>> clock reference registers. Normally, we map the entire address range of >>>> a clock controller (CC) module in the device tree. However, for TCSRCC >>>> where CLKREF_EN registers are located within shared modules like TCSR or >>>> TLMM—we don't own the whole address space, and mapping the full range >>>> can overlap with other devices. >>>> To avoid this, we propose defining the base address as the first >>>> register actually used, and the size to only include up to the last >>>> register we use. This ensures we only map the relevant subblock, >>>> preventing conflicts with other device nodes. >>> >>> Then you need to behave slightly differently: map the full range at the >>> basic device (TLMM, TCSR, etc.) and then create TCSRCC as a child device >>> to that node (and use paren't regmap to access the registers). >>> >> >> Dmitry, I agree that this approach is ideal. However, the current >> hardware implementation isn’t consistent across multiple SoCs, which >> means the driver design also needs to adapt. Given these differences, we >> decided to strictly map only the range of hardware registers that are >> actually used for clocks, rather than the entire module. > > You are writing a driver for the platform, not a generic driver for > all the platforms. > I will map the logical subblock and will update the offsets in the TCSRCC driver. >> >>>> >>>> So want to keep the mapping same from the start of clockref clocks. >>>> >>>>> There's also a laaaarge pool of various TCSR_ registers between >>>>> the previous node and this one.. but we can leave that in case we >>>>> need to describe it in a specific way some day >>>>>> + #clock-cells = <1>; >>>>>> + #reset-cells = <1>; >>>>>> + }; >>>>>> + >>>> >>>> -- >>>> Thanks, >>>> Taniya Das >>>> >>> >> >> -- >> Thanks, >> Taniya Das >> > > -- Thanks, Taniya Das