From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67957C433DF for ; Tue, 19 May 2020 11:07:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3B4E0204EF for ; Tue, 19 May 2020 11:07:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728573AbgESLHP (ORCPT ); Tue, 19 May 2020 07:07:15 -0400 Received: from foss.arm.com ([217.140.110.172]:59122 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726466AbgESLHP (ORCPT ); Tue, 19 May 2020 07:07:15 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 68A4F101E; Tue, 19 May 2020 04:07:14 -0700 (PDT) Received: from [10.37.8.206] (unknown [10.37.8.206]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D27A63F52E; Tue, 19 May 2020 04:07:12 -0700 (PDT) Subject: Re: [PATCH V4 10/17] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR0 register To: anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org References: <1589881254-10082-1-git-send-email-anshuman.khandual@arm.com> <1589881254-10082-11-git-send-email-anshuman.khandual@arm.com> From: Suzuki K Poulose Message-ID: <27be7db7-6098-393c-47fa-65b1ef7766bb@arm.com> Date: Tue, 19 May 2020 12:11:58 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <1589881254-10082-11-git-send-email-anshuman.khandual@arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 05/19/2020 10:40 AM, Anshuman Khandual wrote: > Enable MPAM and SEL2 features bits in ID_AA64PFR0 register as per ARM DDI > 0487F.a specification. > > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Mark Rutland > Cc: Suzuki K Poulose > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > > Suggested-by: Will Deacon > Signed-off-by: Anshuman Khandual > --- > arch/arm64/include/asm/sysreg.h | 2 ++ > arch/arm64/kernel/cpufeature.c | 2 ++ > 2 files changed, 4 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index ea075cc08c8f..638f6108860f 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -645,6 +645,8 @@ > #define ID_AA64PFR0_CSV2_SHIFT 56 > #define ID_AA64PFR0_DIT_SHIFT 48 > #define ID_AA64PFR0_AMU_SHIFT 44 > +#define ID_AA64PFR0_MPAM_SHIFT 40 > +#define ID_AA64PFR0_SEL2_SHIFT 36 > #define ID_AA64PFR0_SVE_SHIFT 32 > #define ID_AA64PFR0_RAS_SHIFT 28 > #define ID_AA64PFR0_GIC_SHIFT 24 > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index ed0c400155c9..39fd6cc64796 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -222,6 +222,8 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { > ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0), I don't see any reason why SEL2 should be strict. Rest looks fine to me. Suzuki