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b=DYY7LrTxIxwnRnXpazSW5iejzTVSd8NcNajuRwfs6rtL9JoudtYohxmLy13y2B7vLW4T6T8SJr5HSDO/UW9JB3vD8ng9X15MNBklTJn6VdC0zEXnYRS7I/TEVu7LWK7zo4HLJE4gI0aysHMB94jnzgOgtV+gXzqWrQWyJ/YyqlM= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from SJ2PR12MB8109.namprd12.prod.outlook.com (2603:10b6:a03:4f5::8) by MW4PR12MB6924.namprd12.prod.outlook.com (2603:10b6:303:207::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9412.13; Mon, 15 Dec 2025 08:03:00 +0000 Received: from SJ2PR12MB8109.namprd12.prod.outlook.com ([fe80::7f35:efe7:5e82:5e30]) by SJ2PR12MB8109.namprd12.prod.outlook.com ([fe80::7f35:efe7:5e82:5e30%4]) with mapi id 15.20.9412.005; Mon, 15 Dec 2025 08:03:00 +0000 Message-ID: <27c2e287-949e-4ae5-a818-49f6d61cba5c@amd.com> Date: Mon, 15 Dec 2025 09:02:53 +0100 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/1] arm64: dts: xilinx: fix zynqmp opp-table-cpu To: Neal Frager , gregkh@linuxfoundation.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, git@amd.com Cc: jguittet@witekio.com, jay.buddhabhatti@amd.com, arun.balaji.kannan@amd.com, senthilnathan.thangaraj@amd.com, thomas.hommel@emerson.com, micheal.saleab@amd.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, peter@korsgaard.com References: <20251111070555.1169130-1-neal.frager@amd.com> Content-Language: en-US From: Michal Simek Autocrypt: addr=michal.simek@amd.com; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?OVA2VlFnNis5eHV6dTNTS1ZpS2RORFFpYzBZeGJidlRhUUprOWpKMmttbCtu?= =?utf-8?B?Ti8reGJQc2dTNjVYYStnMGdaSThvVmg5YWxsNDRjOFgyd01WWXdtZnlFNk5K?= =?utf-8?B?algvV00yUUZFd1U4MFpGNXpxZE5mMjFSODk5V2l0OHN6ekRTS0FUR3lFenNy?= =?utf-8?B?MGdDd2ZWK29HTUtUdndObk51eWpkMXdhWUk5NDhjVURJVUtmVG1Fcnlzam1v?= =?utf-8?B?SHJqVWtxQ1VPekIrdFhqdDhQN0tFTVdGcmZDdVhPUTF2NGNuSGFoZVFjZXpI?= =?utf-8?B?RysyTHBFc0lQYzB4b3FjYktBc2ZoekFuUDVIZEhRNUdXdDQySi9xQmo5cXVl?= =?utf-8?B?Y1Zrcmc1cyt0MGwzWXRvaVJaMHZnUnRSanhLN3FISXVtZElwUXhUYmNvM21Q?= =?utf-8?B?aEgva3JNQjNRS1oycDd1ZnZtQ2pRenNDeERjOVFuYW91NjBXY20xVE94am8w?= =?utf-8?B?bE5HaWhITzJXa2hhQ3B5RjdUd0kzdnlmc21hNXAzc1RmZmU1UndWcCtFRG4x?= =?utf-8?B?RnhSRlllbStVSWJkSlJWSjVzelJpVndPbXNJS2NJN3R4eVZiNEZUU1lsTFJw?= =?utf-8?B?L2VEMHUrV21uVkFtSmNNK2ZsdmdyTWkwUVJabUhQbDBPVHFJdzFBZTlOcXRi?= =?utf-8?B?ZlRZZHZTVThnMnQ3ZUZZdjAwVFE0T1N2ZnhUeGtWUUs0UHNpMVRoYkxmM3Jp?= =?utf-8?B?OUF2RDJQcVRtcjhwd1V2cDRRT1VwUFltcWRpaDdSWjFlSkV5VFJjZ1dVVmRj?= =?utf-8?B?eDlWOFdqVzM3MEdiMk9VdncrU3NrYTVhRWRNTXBGbjRPMFJEUW1mbytpS1g4?= =?utf-8?B?RmljSmlnSHRUbmxIaDFJNi85Zk9UcDRKcmw1bG5Mcnc2d2llWk1RdGtneCtT?= =?utf-8?B?SzhldFpyQ3hMY2JoaWx3RlpITjlxam1jTGYwV3JReUIyUzgrUitpRWZ2TmVn?= =?utf-8?B?UUg3c3l2K2M1all3ZlNUT2h5V0t0L0FGVlpIU1dEK3djamJ4OW5UNVFZVS9W?= =?utf-8?B?RHN3SllLNHh2eXoxck5saXJKU3hEakovZFdtRXJHRDlJaWQzZDFHN2ErUm1D?= =?utf-8?B?SThuOW5RZ1pyUEJmMFdJbExjdVVvbjBLVTdZMVlrSDM4UXJ3OUFOWFlEYjJx?= =?utf-8?B?R0RTWU1LbkFkMHNkMFN3VmZicXJpUXJzU0dkdk5vT0xYcjE2UkV1U2hSTUxt?= =?utf-8?B?RHE1VmxWS0hxbE1QamFKb2ZNNmZpd2dzNlR3bG5pRGtwUldoUE1udi9ILzRo?= =?utf-8?B?bXoybHpybXlSeHc1czZkb09rUmlFbVhITDZsdzFWUk45Ty9BMEJlaVFvUU96?= =?utf-8?B?SHRZNEZLSHZPUy9laEVES3Z6elNtMDZSS1hFY295Y0E3cnMxQ2RUWjhZQTcy?= =?utf-8?B?MWQzSnlHa0d1cmcwQ05XM1ovR2JuNWhWWkFIR3djcjVUZTh3TmZ4MWRMOEdQ?= =?utf-8?B?MkZsTlNiclJ6YW5jS2VjWjNmcWlnOFlGelpDNy9wc09zWkVQUkpuNW1BbjJq?= =?utf-8?B?dXpBNi81OVJkdkRGTWJnOFZMYW9QWVo5Q1NBZlRRMklMMEl6QkFpclNncGxu?= =?utf-8?B?dGpjYUxZTDJLZk9rRjlOdi93Y0pjTStjblpubklacFA1L2didENCTEJQZDVB?= =?utf-8?B?di9VMks3M0lrR2JRVFZ4R3hCc1lDUkF0WlZkMnBBRXk4TUZBdFNKU3U3VnR2?= =?utf-8?B?WGJ6T1Nma1hnbFVCbXJhUnN6RlhLdGovaWlyMkZjSTVESENHYVVOWEFYaElP?= =?utf-8?B?Q3lWNHRHeEtuQmZvUUFMcnNxR25uYXh1U2ZNbmcwTEx5WVBnMDFBdW1HVFdj?= =?utf-8?B?UFlLcG1BUGdGV1V4ZUFMb0JGUmY0QUNlcktpbWk0SlVSRVJIWDlOQm15VWxo?= =?utf-8?B?NmJOQXpSSlJHa1ZnRmFpME5xeXpzK2hSV0NXeWNPbmtYL2F6TEkvQld5STVG?= =?utf-8?B?L2cxbWMrYTU0dUt1QWNYSmRVMUNMVXdsV3NIZGxHdE9wQU1taHJXVU1ZcEJz?= =?utf-8?B?WDUxOXlzSjFndnJtV2hURkVveW12b3ErY3RyRzVDbUhuVk90TkQ4L0pBS3VU?= =?utf-8?B?dnAzS25lM056SmdKV0N1Nnd6MWFyNFgwYTN3M0g4a0tldGROVDV4cDh6Q3pP?= =?utf-8?Q?DRTjPORm0PXqsh0C6vGNwEHp8?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: ef52ad93-4321-4b59-0ce9-08de3bb05d49 X-MS-Exchange-CrossTenant-AuthSource: SJ2PR12MB8109.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2025 08:02:59.9582 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: DVxpzpPLqNiOz/+HEY1McswnQBPAOc9SxWKhoV3R0qZnSoYkLo5ZacGbemwayIPK X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6924 On 11/11/25 08:05, Neal Frager wrote: > Since the following commit, the zynqmp clk driver uses the common > divider_round_rate() when determining the appropriate clock divider for a > requested clock frequency: > https://github.com/torvalds/linux/commit/1fe15be1fb613534ecbac5f8c3f8744f757d237d > > This means that all the calculations will be in kHz when determining the > appropriate clock divider for a given cpufreq request. The problem with this > is that the zynqmp.dtsi and zynqmp-clk-ccf.dtsi files have frequency > definitions in Hz, so when dividing requested values in kHz, errors can occur > with the rounding. > > For example, the current pss_ref_clk frequency is 33333333 Hz which generates > a cpufreq parent clock frequency of 1199999988 Hz which is the same as the > highest opp-table-cpu frequency in the zynqmp.dtsi. > > But if a user requests the value 1199999 kHz as recommended in the available > frequencies: > > root@zynqmp:/sys/kernel/tracing# cat /sys/devices/system/cpu/cpufreq/policy0/scaling_available_frequencies > 299999 399999 599999 1199999 > root@zynqmp:/ # echo 1199999 > /sys/devices/system/cpu/cpufreq/policy0/scaling_setspeed > > The calculation will be: > 1199999988 / 1199999000 = 1.000001 > > This will get rounded up to a divider value of 2 giving the following result. > > root@zynqmp:/ # cat /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq > 599999 > > Also, if a user tries to work around this calculation by using any larger > values, it still will not fix the problem because the driver will use the > largest opp in kHz which leads to the same calculation error. > > User requests 1200000 > root@zynqmp:/ # echo 1200000 > /sys/devices/system/cpu/cpufreq/policy0/scaling_setspeed > > Driver converts any value greater than 1199999 to the largest opp which is > 1199999 and then calculates the divider value with the same calculation. > > The calculation will still be: > 1199999988 / 1199999000 = 1.000001 > > This will get rounded up to a divider value of 2 giving the following result. > > root@zynqmp:/ # cat /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq > 599999 > > This means there is no way to configure the zynqmp for the fastest opp using > the current dtsi files. > > To fix this issue, this patch updates the zynqmp opp-table-cpu and > pss_ref_clk, so the clock rates are calculated correctly. > > root@zynqmp:/sys/kernel/tracing# cat /sys/devices/system/cpu/cpufreq/policy0/scaling_available_frequencies > 300000 400000 600000 1200000 > root@zynqmp:/ # echo 1200000 > /sys/devices/system/cpu/cpufreq/policy0/scaling_setspeed > root@zynqmp:/ # cat /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq > 1200000 > > Signed-off-by: Neal Frager > --- > V1->V2: > - The clock-latency-ns and opp-microvolt values did not change, so simplify > the patch by only changing the opp-hz values in decimal format. > V2->V3: > - Improved commit explanation > - Added pss_ref_clk frequency change to the patch > --- > arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 2 +- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 16 ++++++++-------- > 2 files changed, 9 insertions(+), 9 deletions(-) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi > index 52e122fc7c9e..482f432ba7f3 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi > @@ -14,7 +14,7 @@ pss_ref_clk: pss-ref-clk { > bootph-all; > compatible = "fixed-clock"; > #clock-cells = <0>; > - clock-frequency = <33333333>; > + clock-frequency = <33333000>; > clock-output-names = "pss_ref_clk"; > }; > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index 938b014ca923..dd9bd39f61e8 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -103,23 +103,23 @@ CPU_SLEEP_0: cpu-sleep-0 { > cpu_opp_table: opp-table-cpu { > compatible = "operating-points-v2"; > opp-shared; > - opp00 { > - opp-hz = /bits/ 64 <1199999988>; > + opp-1200000000 { > + opp-hz = /bits/ 64 <1200000000>; > opp-microvolt = <1000000>; > clock-latency-ns = <500000>; > }; > - opp01 { > - opp-hz = /bits/ 64 <599999994>; > + opp-600000000 { > + opp-hz = /bits/ 64 <600000000>; > opp-microvolt = <1000000>; > clock-latency-ns = <500000>; > }; > - opp02 { > - opp-hz = /bits/ 64 <399999996>; > + opp-400000000 { > + opp-hz = /bits/ 64 <400000000>; > opp-microvolt = <1000000>; > clock-latency-ns = <500000>; > }; > - opp03 { > - opp-hz = /bits/ 64 <299999997>; > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > opp-microvolt = <1000000>; > clock-latency-ns = <500000>; > }; Applied. M