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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae6e8264fbcsm1437115666b.75.2025.07.17.13.34.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 17 Jul 2025 13:34:36 -0700 (PDT) Message-ID: <27e4a27d-6e91-4e91-b55f-d6aa4a5be800@oss.qualcomm.com> Date: Thu, 17 Jul 2025 22:34:33 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 08/15] arm64: dts: qcom: x1e80100: Add MIPI CSI PHY nodes To: Bryan O'Donoghue , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Konrad Dybcio , Vladimir Zapolskiy Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org References: <20250711-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-0-0bc5da82f526@linaro.org> <20250711-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-8-0bc5da82f526@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250711-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-8-0bc5da82f526@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE3MDE4MSBTYWx0ZWRfXy6QhK2mFL/7a NwWre8iJ0OYzl8G5OYDeA7DUc304U0GOYpEe3SevmXEd6FashSSljqYY8eB18LdSQbxVMC+TE4v kWf6O/xDN/VmkAsdtvVGB6e/ndocYGJ4xv7NUUMc3Yn/lE5Q8NDnhibpXlG27REtIhXN7BD4KZ9 5/akDMymlkmB4pQAuW460DK4fcrt2jM0YJynI60Dcs7mAswCB7wRUMkYWqaxbSSOaENkeOzMkMq CfAkaCqhzVW+q7Wh4vKw6tpLfKsfVhWCl/cB9iZp9KGTslqT0bonjS10hDiHbJ8evkI3jfZrngl 5TRSQ6oGnwBKKghsxVYG+aAfdt+IA1+qTx9zdbuLZINVk2pUWSZDZ31PGeaG+M7FkLQKOYjsKJC Ve5MKlUaiolc92EN0beb13J73bcqDguVoWn5LTbXKryfZ364R54QxHwv+zEyzEeg9fROa6wX X-Proofpoint-GUID: ATCjCjayEcId9w6sfMXHwt6jN5TGDdzh X-Authority-Analysis: v=2.4 cv=SZT3duRu c=1 sm=1 tr=0 ts=68795e5e cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=KKAkSRfTAAAA:8 a=jM4f9QFlUBkeW2BXBzcA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: ATCjCjayEcId9w6sfMXHwt6jN5TGDdzh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-17_03,2025-07-17_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=999 mlxscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 adultscore=0 impostorscore=0 malwarescore=0 phishscore=0 spamscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507170181 On 7/11/25 2:58 PM, Bryan O'Donoghue wrote: > Add csiphy nodes for > > - csiphy0 > - csiphy1 > - csiphy2 > - csiphy4 > > The irregular naming of the PHYs comes directly from the hardware which for > whatever reason skipped csiphy3. > > Separating the nodes from CAMSS as we have done with the sensor I2C bus aka > the CCI interface is justified since the CSIPHYs have their own pinouts and > voltage rails. > > Signed-off-by: Bryan O'Donoghue > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 88 ++++++++++++++++++++++++++++++++++ > 1 file changed, 88 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index 41245e8592f78edf141141f2f5b7c5b841318f46..e385d6f329616360e089ba352be450c9eca6aab6 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -5244,6 +5244,94 @@ cci1_i2c1: i2c-bus@1 { > }; > }; > > + csiphy0: csiphy@ace4000 { > + compatible = "qcom,x1e80100-mipi-csi2-combo-phy"; > + reg = <0 0x0ace4000 0 0x2000>; > + > + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CSIPHY0_CLK>, > + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; > + clock-names = "camnoc_axi", > + "cpas_ahb", > + "csiphy", > + "csiphy_timer"; > + > + interrupts = ; > + > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; I realize it may not be easy to test their functionality without the rest of CAMSS being enabled, but are the CSIPHY's registers accessible without the TOP GDSC being enabled? Konrad