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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5f703545218sm8711952a12.53.2025.04.30.08.36.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Apr 2025 08:36:44 -0700 (PDT) Message-ID: <281ab1b6-498e-4b29-9e15-19b5aae25342@oss.qualcomm.com> Date: Wed, 30 Apr 2025 17:36:42 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFT v6 2/5] drm/msm/adreno: Add speedbin data for SM8550 / A740 To: neil.armstrong@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio References: <20250430-topic-smem_speedbin_respin-v6-0-954ff66061cf@oss.qualcomm.com> <20250430-topic-smem_speedbin_respin-v6-2-954ff66061cf@oss.qualcomm.com> <13cd20c6-f758-45ff-82d1-4fd663d1698c@linaro.org> <886d979d-c513-4ab8-829e-4a885953079a@oss.qualcomm.com> <98a4ad20-c141-4280-801e-015dafd1fb39@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=G5AcE8k5 c=1 sm=1 tr=0 ts=6812438e cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=KKAkSRfTAAAA:8 a=uyuhvXrvZAXgkk1q3UwA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDMwMDExMSBTYWx0ZWRfX7mun5eXjvkR6 XG//5Op/ltry+yM4tJy4zWqgY7vE45U5P5A2+j5goW1nW8QMMGkUQXUyxpxgt3mm2AdKmaFny0E 0v7QiIg2DhQxKKEFTqrwn8zN/ME/7egpkJpTO949TbfznJjaOUwoeAvF3jji/SghqaCPGj2vT31 trTNJBLnQZtZaE4XhjaB9/xI6VvCom8D7cdoGOMag767lXbuHhyj0iStKkkIuk5fYYoP2bnvnoF KK8C4qyS0qNwm5wFYV2IgfuTfvsoWWHDTeyuWo26/0C0FvgjKEMU1MJ8pXZdlo9hBMfGO8bpp5O A0otqu9GuO9ioT6gjKhZlzeR7Q/NyUB9R7XOsK+qVAjH73mQwKf/wd54gq8+/wLo/LW5wmZ2vJS n/0NNNpLHU+8z0wVKfcm1o2EXHhzMimifL6TpIzEFWNwATzqYJMrrPixUFT7nwAzF/jvcy8q X-Proofpoint-GUID: K5hbix3mIlIcCRPVaQWfhtTwfC4W1vaV X-Proofpoint-ORIG-GUID: K5hbix3mIlIcCRPVaQWfhtTwfC4W1vaV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-30_04,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 impostorscore=0 phishscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 mlxscore=0 malwarescore=0 suspectscore=0 clxscore=1015 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504300111 On 4/30/25 4:49 PM, neil.armstrong@linaro.org wrote: > On 30/04/2025 15:09, Konrad Dybcio wrote: >> On 4/30/25 2:49 PM, neil.armstrong@linaro.org wrote: >>> On 30/04/2025 14:35, Konrad Dybcio wrote: >>>> On 4/30/25 2:26 PM, neil.armstrong@linaro.org wrote: >>>>> Hi, >>>>> >>>>> On 30/04/2025 13:34, Konrad Dybcio wrote: >>>>>> From: Konrad Dybcio >>>>>> >>>>>> Add speebin data for A740, as found on SM8550 and derivative SoCs. >>>>>> >>>>>> For non-development SoCs it seems that "everything except FC_AC, FC_AF >>>>>> should be speedbin 1", but what the values are for said "everything" are >>>>>> not known, so that's an exercise left to the user.. >>>>>> >>>>>> Reviewed-by: Dmitry Baryshkov >>>>>> Signed-off-by: Konrad Dybcio >>>>>> --- >>>>>>     drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 8 ++++++++ >>>>>>     1 file changed, 8 insertions(+) >>>>>> >>>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>>> index 53e2ff4406d8f0afe474aaafbf0e459ef8f4577d..61daa331567925e529deae5e25d6fb63a8ba8375 100644 >>>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>>> @@ -11,6 +11,9 @@ >>>>>>     #include "a6xx.xml.h" >>>>>>     #include "a6xx_gmu.xml.h" >>>>>>     +#include >>>>>> +#include >>>>>> + >>>>>>     static const struct adreno_reglist a612_hwcg[] = { >>>>>>         {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, >>>>>>         {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, >>>>>> @@ -1431,6 +1434,11 @@ static const struct adreno_info a7xx_gpus[] = { >>>>>>             }, >>>>>>             .address_space_size = SZ_16G, >>>>>>             .preempt_record_size = 4192 * SZ_1K, >>>>>> +        .speedbins = ADRENO_SPEEDBINS( >>>>>> +            { ADRENO_SKU_ID(SOCINFO_FC_AC), 0 }, >>>>>> +            { ADRENO_SKU_ID(SOCINFO_FC_AF), 0 }, >>>>>> +            /* Other feature codes (on prod SoCs) should match to speedbin 1 */ >>>>> >>>>> I'm trying to understand this sentence. because reading patch 4, when there's no match >>>>> devm_pm_opp_set_supported_hw() is simply never called so how can it match speedbin 1 ? >>>> >>>> What I'm saying is that all other entries that happen to be possibly >>>> added down the line are expected to be speedbin 1 (i.e. BIT(1)) >>>> >>>>> Before this change the fallback was speedbin = BIT(0), but this disappeared. >>>> >>>> No, the default was to allow speedbin mask ~(0U) >>> >>> Hmm no: >>> >>>      supp_hw = fuse_to_supp_hw(info, speedbin); >>> >>>      if (supp_hw == UINT_MAX) { >>>          DRM_DEV_ERROR(dev, >>>              "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", >>>              speedbin); >>>          supp_hw = BIT(0); /* Default */ >>>      } >>> >>>      ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); >>>      if (ret) >>>          return ret; >> >> Right, that's my own code even.. >> >> in any case, the kernel can't know about the speed bins that aren't >> defined and here we only define bin0, which doesn't break things >> >> the kernel isn't aware about hw with bin1 with or without this change >> so it effectively doesn't matter > > But it's regression for the other platforms, where before an unknown SKU > mapped to supp_hw=BIT(0) > > Not calling devm_pm_opp_set_supported_hw() is a major regression, > if the opp-supported-hw is present, the OPP will be rejected: A comment in patch 4 explains that. We can either be forwards or backwards compatible (i.e. accept a limited amount of speedbin_in_driver x speedbin_in_dt combinations) Konrad