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charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: dXXxUyHXWwjBzGmoM1TjFRX_qOYvubw8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI0MDEyNyBTYWx0ZWRfX3AJIAg4521JJ zaBYYxkt/VeNvhDD0G5PiGZP8xfMhMnkqeypiIURii44unIacxgDb4rhLnuqcufApACFE05bL/t S48T0YPyx9LeVOPw+FKW2nNiUsOI1RzwfnRuyE+HWXJrY4F/4RXVG0M6UIkXK0r/wItxDLucoQ/ /3ZFvAvQdhfYrf/AfqC+z/PPjFLhgkZfvbtLY0YmLNgjMArXjD7g1vPIhbd9LhQAmIRruJBeyR4 1MEL9FyIfn43bcOhyUPuYeNLNh6DVHdkcArKMYvN5noqGCHpVT/FdMv1sQPEb6XYn42/Lx+rupU ZzcxN+iz3fTNdX8+V77Nds5b+jq0dB0u3aODzdiOOZRexVMR7K++sJHyyfHa8QxqZaW3mYgLF5G 38Pk7jgZMTz76QJHicWw+755nHXteaMj3wFhmr/JqaRO/7tCXWhpqhESwKZvLKxbBrXGjKOi X-Authority-Analysis: v=2.4 cv=Q+fS452a c=1 sm=1 tr=0 ts=6882632b cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=pSIa2sKh8ADkebnh61Ypzg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=KKAkSRfTAAAA:8 a=bFu9_hsFAaDUiof9l7EA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: dXXxUyHXWwjBzGmoM1TjFRX_qOYvubw8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-24_03,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=999 suspectscore=0 spamscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507240127 On 7/24/2025 8:14 PM, Neil Armstrong wrote: > On 24/07/2025 16:35, Akhil P Oommen wrote: >> On 7/21/2025 6:05 PM, Neil Armstrong wrote: >>> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along >>> the Frequency and Power Domain level, but by default we leave the >>> OPP core scale the interconnect ddr path. >>> >>> Declare the Bus Control Modules (BCMs) and the corresponding parameters >>> in the GPU info struct to allow the GMU to vote for the bandwidth. >>> >>> Signed-off-by: Neil Armstrong >>> --- >>>   drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++ >>>   1 file changed, 11 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/ >>> drm/msm/adreno/a6xx_catalog.c >>> index >>> 00e1afd46b81546eec03e22cda9e9a604f6f3b60..b313505e665ba50e46f2c2b7c34925b929a94c31 100644 >>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = { >>>               .pwrup_reglist = &a7xx_pwrup_reglist, >>>               .gmu_chipid = 0x7050001, >>>               .gmu_cgc_mode = 0x00020202, >>> +            .bcms = (const struct a6xx_bcm[]) { >>> +                { .name = "SH0", .buswidth = 16 }, >>> +                { .name = "MC0", .buswidth = 4 }, >>> +                { >>> +                    .name = "ACV", >>> +                    .fixed = true, >>> +                    .perfmode = BIT(2), >>> +                    .perfmode_bw = 10687500, >> >> This configurations should be similar to X1-45. > > Including the perfmode bit ? > > +                    .perfmode = BIT(3), > +                    .perfmode_bw = 16500000, > Yes, both. -Akhil > > Neil > >> >> -Akhil >> >>> +                }, >>> +                { /* sentinel */ }, >>> +            }, >>>           }, >>>           .preempt_record_size = 4192 * SZ_1K, >>>           .speedbins = ADRENO_SPEEDBINS( >>> >>> --- >>> base-commit: 97987520025658f30bb787a99ffbd9bbff9ffc9d >>> change-id: 20250721-topic-x1e80100-gpu-bwvote-9fc4690fe5e3 >>> >>> Best regards, >> >