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[83.9.32.99]) by smtp.gmail.com with ESMTPSA id b7-20020ac24107000000b004db297957e8sm833847lfi.305.2023.02.27.00.46.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Feb 2023 00:46:35 -0800 (PST) Message-ID: <2852ca77-81fd-0e39-5030-d9d0f483ea0a@linaro.org> Date: Mon, 27 Feb 2023 09:46:33 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v2 08/13] ARM: dts: qcom: sdx55: List the property values vertically Content-Language: en-US To: Manivannan Sadhasivam , andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org References: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> <20230224105906.16540-9-manivannan.sadhasivam@linaro.org> From: Konrad Dybcio In-Reply-To: <20230224105906.16540-9-manivannan.sadhasivam@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 24.02.2023 11:59, Manivannan Sadhasivam wrote: > To align with the rest of the devicetree files and the relative properties, > let's list the values of properties such as {reg/clock/interrupt}-names > vertically. > > Suggested-by: Konrad Dybcio > Signed-off-by: Manivannan Sadhasivam > --- Reviewed-by: Konrad Dybcio Konrad > arch/arm/boot/dts/qcom-sdx55.dtsi | 23 ++++++++++++++++++----- > 1 file changed, 18 insertions(+), 5 deletions(-) > > diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi > index b411c4ae34c3..61fdd601fc26 100644 > --- a/arch/arm/boot/dts/qcom-sdx55.dtsi > +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi > @@ -393,7 +393,11 @@ pcie_ep: pcie-ep@1c00000 { > <0x40001000 0x1000>, > <0x40200000 0x100000>, > <0x01c03000 0x3000>; > - reg-names = "parf", "dbi", "elbi", "atu", "addr_space", > + reg-names = "parf", > + "dbi", > + "elbi", > + "atu", > + "addr_space", > "mmio"; > > qcom,perst-regs = <&tcsr 0xb258 0xb270>; > @@ -405,12 +409,18 @@ pcie_ep: pcie-ep@1c00000 { > <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, > <&gcc GCC_PCIE_SLEEP_CLK>, > <&gcc GCC_PCIE_0_CLKREF_CLK>; > - clock-names = "aux", "cfg", "bus_master", "bus_slave", > - "slave_q2a", "sleep", "ref"; > + clock-names = "aux", > + "cfg", > + "bus_master", > + "bus_slave", > + "slave_q2a", > + "sleep", > + "ref"; > > interrupts = , > ; > - interrupt-names = "global", "doorbell"; > + interrupt-names = "global", > + "doorbell"; > reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; > wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; > resets = <&gcc GCC_PCIE_BCR>; > @@ -434,7 +444,10 @@ pcie_phy: phy@1c07000 { > <&gcc GCC_PCIE_CFG_AHB_CLK>, > <&gcc GCC_PCIE_0_CLKREF_CLK>, > <&gcc GCC_PCIE_RCHNG_PHY_CLK>; > - clock-names = "aux", "cfg_ahb", "ref", "refgen"; > + clock-names = "aux", > + "cfg_ahb", > + "ref", > + "refgen"; > > resets = <&gcc GCC_PCIE_PHY_BCR>; > reset-names = "phy";