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Tue, 30 Dec 2025 01:03:14 -0800 (PST) X-Google-Smtp-Source: AGHT+IEbAGF2db+VKOhlDQMrg8j2Qk0RrNBOlo/z6NG5BVl4tukVcG15xd/QngN7ITvfdf94rAAulg== X-Received: by 2002:a05:6a20:1588:b0:366:14b0:4b18 with SMTP id adf61e73a8af0-3769ff1a89amr34483814637.35.1767085393974; Tue, 30 Dec 2025 01:03:13 -0800 (PST) Received: from [10.217.216.105] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c1e7961fbb9sm27338846a12.2.2025.12.30.01.03.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 30 Dec 2025 01:03:13 -0800 (PST) Message-ID: <28751331-d298-4cd6-b98a-c125e3f75eda@oss.qualcomm.com> Date: Tue, 30 Dec 2025 14:33:07 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V1 3/4] arm64: dts: qcom: hamoa: Add UFS nodes for hamoa SoC To: Konrad Dybcio , vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, martin.petersen@oracle.com, andersson@kernel.org, konradybcio@kernel.org, taniya.das@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, nitin.rawat@oss.qualcomm.com References: <20251229060642.2807165-1-pradeep.pragallapati@oss.qualcomm.com> <20251229060642.2807165-4-pradeep.pragallapati@oss.qualcomm.com> <986facd7-92e7-4d29-a196-d49cd9f3d35f@oss.qualcomm.com> Content-Language: en-US From: Pradeep Pragallapati In-Reply-To: <986facd7-92e7-4d29-a196-d49cd9f3d35f@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjMwMDA4MCBTYWx0ZWRfX/dSwXpQnMI8p Tm+sfoGak7pWON7suFkWNJf9uK4UzATyiGbbNbExZN5Nz+Vzq7j80LFUWF7hXXEdNvb1MuDpsNP iBW4G1VAHLqETesEqBWqru6fKg/T9li6F9zwb9Ri4n7Y5+S/DW41BallhdjLtiq1YctXNeOzkx2 twOLpZPtPXyMUdDqYNm9JWKYzikEcb20s7V+3/eGVYWOASwtQvb4XaZKb5x+nrl9Sxchti3AIMa odkX9XIVG21+W8x3TJWawux2DDTWaHB6EzYMjrPjSzUafNcdUVj1robq3m7iecojrYu3pDmPPC1 /l4boowJEX6v+jN2p8HBxpJu7RD9dht6bp7ORF/5KTR0i5MA6WCkny05+IZKmxN4RrNsf7ZXyVu 6JjsF5XL97kK/DZoPwYNOcZaMBaPNulbAy5LXDYfy1zFZyurzPNbE3SMVfV0WG8uqMk5F6XFIeI Jt1JuNErgWplAC3W50Q== X-Proofpoint-ORIG-GUID: yovDAbm9DYXhCuN4pu_8xnNPz5YwLmru X-Proofpoint-GUID: yovDAbm9DYXhCuN4pu_8xnNPz5YwLmru X-Authority-Analysis: v=2.4 cv=FJ0WBuos c=1 sm=1 tr=0 ts=69539553 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=XVHmVgbNHDG9-czVeNYA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-29_07,2025-12-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 impostorscore=0 spamscore=0 phishscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512300080 On 12/29/2025 5:45 PM, Konrad Dybcio wrote: > On 12/29/25 7:06 AM, Pradeep P V K wrote: >> Add UFS host controller and PHY nodes for hamoa SoC. >> >> Signed-off-by: Pradeep P V K >> --- >> arch/arm64/boot/dts/qcom/hamoa.dtsi | 119 +++++++++++++++++++++++++++- >> 1 file changed, 118 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi >> index bb7c14d473c9..340b907657be 100644 >> --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi >> +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi >> @@ -834,7 +834,10 @@ gcc: clock-controller@100000 { >> <0>, >> <0>, >> <0>, >> - <0>; >> + <0>, >> + <&ufs_mem_phy 0>, >> + <&ufs_mem_phy 1>, >> + <&ufs_mem_phy 2>; > This patch cannot be applied as-is (needs GCC bindings changes first) > which you didn't mention in the cover letter. > > If it were picked up, we'd get DTB valdation errors. ok, i will mention the link to GCC postings in my cover letter in my next patchset. > >> >> power-domains = <&rpmhpd RPMHPD_CX>; >> #clock-cells = <1>; >> @@ -3845,6 +3848,120 @@ pcie4_phy: phy@1c0e000 { >> status = "disabled"; >> }; >> >> + ufs_mem_phy: phy@1d80000 { >> + compatible = "qcom,hamoa-qmp-ufs-phy", "qcom,sm8550-qmp-ufs-phy"; >> + reg = <0x0 0x1d80000 0x0 0x2000>; > Please pad the address part to 8 hex digits, so 0x1d80000 -> 0x01d80000 > > [...] ack. i will update in my next patchset. > >> + ufs_mem_hc: ufs@1d84000 { >> + compatible = "qcom,hamoa-ufshc", "qcom,sm8550-ufshc", "qcom,ufshc", >> + "jedec,ufs-2.0"; > 1 a line would be neater, perhaps in the node above too sure, will update in my next patchset. > >> + reg = <0x0 0x1d84000 0x0 0x3000>; > Similar case as before ack. will update in my next patchset. > > lgtm otherwise > > Konrad