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Tue, 03 Dec 2024 17:11:41 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B3HBfet023736 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 3 Dec 2024 17:11:41 GMT Received: from [10.216.52.53] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 3 Dec 2024 09:11:36 -0800 Message-ID: <289e7959-8eae-4598-899c-16c67e66d4e9@quicinc.com> Date: Tue, 3 Dec 2024 22:41:32 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 2/2] arm64: dts: qcom: sa8775p: Add support for clock controllers To: Bjorn Andersson CC: Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , , , Bartosz Golaszewski , , , , , Ajit Pandey References: <20241025-sa8775p-mm-v4-resend-patches-v6-0-329a2cac09ae@quicinc.com> <20241025-sa8775p-mm-v4-resend-patches-v6-2-329a2cac09ae@quicinc.com> <9e0f200b-53dd-4dbf-8b0d-1a2f576d3e3f@oss.qualcomm.com> <97c6ef74-7ce8-4e67-85f9-d5452678f45f@quicinc.com> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: aqY4RaDbBV-cpQnsLrY4ijAgKk-dkQIm X-Proofpoint-GUID: aqY4RaDbBV-cpQnsLrY4ijAgKk-dkQIm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=816 clxscore=1015 phishscore=0 adultscore=0 suspectscore=0 malwarescore=0 spamscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412030144 On 12/3/2024 9:02 PM, Bjorn Andersson wrote: > On Tue, Dec 03, 2024 at 10:04:13AM +0530, Taniya Das wrote: >> >> >> On 10/26/2024 12:12 AM, Konrad Dybcio wrote: >>> On 25.10.2024 8:42 PM, Konrad Dybcio wrote: >>>> On 25.10.2024 10:52 AM, Taniya Das wrote: >>>>> Add support for video, camera, display0 and display1 clock controllers >>>>> on SA8775P. The dispcc1 will be enabled based on board requirements. >>> >>> Actually, why would that be? CCF should park it gracefully with >>> unused cleanup >>> >> >> Yes, CCF should take care to cleanup. But I am of an opinion that as we are >> aware that this platform do not require the dispcc1 so we could avoid the >> clock driver initialization and help in boot KPI. >> > > Does that imply that we're guaranteed that the bootloader will never > configure any clocks in dispcc1 that needs to be gracefully parked from > the OS? Is this guaranteed to be the case for all QCS9100 boards? > Yes, bootloader will never use DISPCC1. > IMHO we should default to correctness, and then make product-specific > boot time optimizations from that starting point. > As I was sure it will not be used on this board, so I left it disabled. > Regards, > Bjorn > >>> Konrad >>> >>>>> >>>>> Reviewed-by: Jagadeesh Kona >>>>> Signed-off-by: Taniya Das >>>>> --- >>>> >>>> Reviewed-by: Konrad Dybcio >>>> >>>> Konrad >> >> -- >> Thanks & Regards, >> Taniya Das. -- Thanks & Regards, Taniya Das.