From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5086E230BF2; Thu, 19 Jun 2025 07:55:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750319757; cv=none; b=WXrY04R3PhY69a6AGBOufBIHn2uuDpFgslrJa3Ak4JvIpkqcWmJjX06cFHGrZrP/cn2Xp9+XcfrJrwIOKQE/zH38JnN+HrWtoNOBs87yL/c7WHZMOWMprrSt8XNfQdLsGo6fGnFxu1sdZVdvn3QtDV384CdItyswLXlxXnjv/Fo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750319757; c=relaxed/simple; bh=CpwCTD9AnUzXrbQp+d9zubfUboByeErtnwKYNnZJ0Js=; h=Message-ID:Date:MIME-Version:Subject:To:CC:References:From: In-Reply-To:Content-Type; b=Bk6nq/XDDpRoEUdifEzir/5K2HaspSu2TCQDTciRj0relt0QT3SYUGQHjBmQxsgCFOKJerNKmsoEV86RpVtww9/QzJe3+u3Z203ahX8PuxxlxF8YkqfgXqR9xAM87Tem1CzCGnZ/pV5cWszFjvgTbxcloKsIQK+JsqJlJ4X7vlM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=aAk3ld15; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="aAk3ld15" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 55J7tlWX336308; Thu, 19 Jun 2025 02:55:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1750319747; bh=bKV7bT5H8Ss8TSiS7uA6G43ZL43gAMDND/KK9ixN5Mw=; h=Date:Subject:To:CC:References:From:In-Reply-To; b=aAk3ld15E3n6L6zqIsqMRoNXNgNjmPwnDcRR7GNPYGAIkeCz0LbMUH6NEMZ6ro2kb 907wITu307DEzC9OxvXV/FyErbsVKvS9mrgXQA1UXLhUziedAPXHz+f0rzA6Cl4T8M /58xKvPW2uDjRGpQ1rcTrgADVd55jbZC5stGAaY8= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 55J7tlTr3513825 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 19 Jun 2025 02:55:47 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 19 Jun 2025 02:55:47 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 19 Jun 2025 02:55:47 -0500 Received: from [172.24.227.245] (uda0132425.dhcp.ti.com [172.24.227.245]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 55J7th2X764414; Thu, 19 Jun 2025 02:55:44 -0500 Message-ID: <28c88a78-fe34-4595-b260-c6cc40897bc1@ti.com> Date: Thu, 19 Jun 2025 13:25:43 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] arm64: dts: ti: k3-am642-evm-pcie0-ep: Add boot phase tag to "pcie0_ep" To: Hrushikesh Salunke , , , , , CC: , , , , References: <20250610054920.2395509-1-h-salunke@ti.com> <98e04654-a693-494d-9f60-930b6a4cd84a@ti.com> From: Vignesh Raghavendra Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea On 12/06/25 15:46, Hrushikesh Salunke wrote: > > > On 11/06/25 14:17, Hrushikesh Salunke wrote: >> >> >> On 11/06/25 14:14, Vignesh Raghavendra wrote: >>> >>> >>> On 10/06/25 11:19, Hrushikesh Salunke wrote: >>>> AM64X SoC has one instance of PCIe which is PCIe0. To support PCIe boot >>>> on AM64X SoC, PCIe0 needs to be in endpoint mode and it needs to be >>>> functional at all stages of PCIe boot process. Thus add the >>>> "bootph-all" boot phase tag to "pcie0_ep" device tree node. >>>> >>>> Signed-off-by: Hrushikesh Salunke >>>> --- >>>> This patch is based on commit >>>> 475c850a7fdd Add linux-next specific files for 20250606 >>>> >>>> Changes since v1 >>>> As per feedback from Nishanth, changed the position of "bootph-all" >>>> tag, according to ordering rules for device tree properties. >>>> >>>> v1 : https://lore.kernel.org/ >>>> all/20250609115930.w2s6jzg7xii55dlu@speckled/ >>>> >>>>   arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso | 1 + >>>>   1 file changed, 1 insertion(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso b/ >>>> arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso >>>> index 432751774853..a7e8d4ea98ac 100644 >>>> --- a/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso >>>> +++ b/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso >>>> @@ -46,6 +46,7 @@ pcie0_ep: pcie-ep@f102000 { >>>>           max-functions = /bits/ 8 <1>; >>>>           phys = <&serdes0_pcie_link>; >>>>           phy-names = "pcie-phy"; >>>> +        bootph-all; >>>>           ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; >>>>       }; >>>>   }; >>> >>> Are the patches for PCIe boot support merged to U-Boot or such other >>> bootloader repo? >>> No, they are not in the U-Boot yet. I will be posting patches for PCIe >> boot support for U-Boot this week. >> > > I have posted Patch series for the PCIe boot support in Uboot. Great, but dont you need bootph-all in dependent nodes as well such as serdes0_pcie_link pcie0_ctrl? how does this work otherwise? > > 1.https://patchwork.ozlabs.org/project/uboot/ > patch/20250612084910.3457060-1-h-salunke@ti.com/ > 2. https://patchwork.ozlabs.org/project/uboot/ > cover/20250612085023.3457117-1-h-salunke@ti.com/ > 3. https://patchwork.ozlabs.org/project/uboot/ > cover/20250612085534.3457522-1-h-salunke@ti.com/ > > > Regards, > Hrushikesh. -- Regards Vignesh https://ti.com/opensource