From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C01FE37C926 for ; Sun, 2 Aug 2026 16:15:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785687313; cv=none; b=ZNYWvw6ApRpBgi8TmvJe7w+zdHmxWJwGtl3duIoFirT+8NInL5NRCvwba8mUpj0k/sEBfnaARu4EaBuWPDg/aWOAzKJHYFcz+a+eJVHV8XE3hWKOZjVCfsTwyKQUkgMVoUSykLgykz5UiRLG3Q2Xe/LtPuzUQN6sc0Gi9IzkJqg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785687313; c=relaxed/simple; bh=CHLXH6vm8D/jpSTUCD9Er82OAlILHeLfp84wIriLHC8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NYXkhMXAcyIVCcKRtiWAS0liSDCKIjFHl0u5zLrfgAqiSlNzbx10Tsc3QA2XtYzTAAKLpEfw0tf1QdWTQWb1CRsqIar5/4sjFp2DlWttcHe3auuIGz3mRJgbale/mcVeqEr2ban9IQ9yRdKVBPdeTiNKQvu6GySQUqrxoQJhU9M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YdqT7o3z; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YdqT7o3z" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1785687311; x=1817223311; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CHLXH6vm8D/jpSTUCD9Er82OAlILHeLfp84wIriLHC8=; b=YdqT7o3z/x3gAg4jaoMXPpqvZHoVUuz8FqFyr+4B2Eks0Agd58AetCLU 6ODwhLToAoeBoGE37AF4fLWfOmQyMF9R0qZoav5efD0r+lx0ABa5Q139t P6goK5quwbmfmLYAHRIGfus8jStNqMSXkwWbOMbKKEy2k9J4vXZjbnzaI ZijgyD/a6Me7uesoawnLrJdz1gwB/Jf3zVLxlBfB1dbPX0jbL0FzgMuHY 5b4kEiew5KLihDN33m7l2gkxNhmOana2qJeryhnlHX1oPvVBNMj0455YO Mua/omiewD1H4BosC/4jXFTe4mY7mQO+BUSv3Kdma5S4qDN3VwOomjCR9 A==; X-CSE-ConnectionGUID: fxNMKo8TSyOsooHUAUY3sw== X-CSE-MsgGUID: EHlXqaSvTaCfhODpQtjWIw== X-IronPort-AV: E=McAfee;i="6800,10657,11863"; a="89915493" X-IronPort-AV: E=Sophos;i="6.25,200,1779174000"; d="scan'208";a="89915493" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Aug 2026 09:15:11 -0700 X-CSE-ConnectionGUID: 6APw7u/KT/mSgKOcfp/tpg== X-CSE-MsgGUID: 47wkPUP6R5qKTulhl7nGNQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,200,1779174000"; d="scan'208";a="261622181" Received: from chenyu-dev.sh.intel.com ([10.239.62.107]) by orviesa009.jf.intel.com with ESMTP; 02 Aug 2026 09:15:08 -0700 From: Chen Yu To: Reinette Chatre , Tony Luck Cc: Ben Horgan , "James Morse" , Dave Martin , Babu Moger , Fenghua Yu , Borislav Petkov , Thomas Gleixner , "Dave Hansen" , Peter Newman , chen.yu@linux.dev, x86@kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 10/31] Revert "x86/resctrl: NOT_FOR_INCLUSION: Example support for multiple controls" Date: Mon, 3 Aug 2026 00:05:26 +0800 Message-Id: <28dce1fe8267f698866b52b763976bc199442fe9.1785680802.git.yu.c.chen@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This reverts commit 37557cac804539e802e887a320e85c7a916a0bb9. Signed-off-by: Chen Yu --- arch/x86/kernel/cpu/resctrl/core.c | 115 ++++++----------------------- 1 file changed, 21 insertions(+), 94 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index 07d669e6e11b..1357f3e5ebd3 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -53,8 +53,6 @@ bool rdt_alloc_capable; static void mba_wrmsr_intel(struct msr_param *m); static void cat_wrmsr(struct msr_param *m); static void mba_wrmsr_amd(struct msr_param *m); -static void update_temporary_max(struct msr_param *m); -static void update_temporary_min(struct msr_param *m); #define ctrl_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.controls) #define mon_domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.mon_domains) @@ -182,47 +180,10 @@ static inline void cache_alloc_hsw_probe(void) rdt_alloc_capable = true; } -static __init bool __temporary_multiple_mba_intel_controls(struct rdt_resource *r, - struct resctrl_hw_ctrl *hw_ctrl, - u32 ecx, u32 max_delay, - enum resctrl_ctrl_name name) -{ - hw_ctrl->r_ctrl.scope = RESCTRL_L3_CACHE; - hw_ctrl->r_ctrl.type = RESCTRL_CTRL_SCALAR; - hw_ctrl->r_ctrl.name = RESCTRL_CTRL_NAME_DEF; - INIT_LIST_HEAD(&hw_ctrl->r_ctrl.domains); - - hw_ctrl->r_ctrl.membw.max_bw = MAX_MBA_BW; - hw_ctrl->r_ctrl.membw.min_bw = MAX_MBA_BW - max_delay; - hw_ctrl->r_ctrl.membw.bw_gran = MAX_MBA_BW - max_delay; - - hw_ctrl->r_ctrl.membw.resolution = 100; - hw_ctrl->r_ctrl.membw.tolerance = 5; - hw_ctrl->r_ctrl.membw.scale = 1; - hw_ctrl->r_ctrl.membw.unit = RESCTRL_CTRL_UNIT_ALL; - - hw_ctrl->r_ctrl.name = name; - - switch (name) { - case RESCTRL_CTRL_NAME_DEF: - hw_ctrl->msr_base = MSR_IA32_MBA_THRTL_BASE; - hw_ctrl->msr_update = mba_wrmsr_intel; - break; - case RESCTRL_CTRL_NAME_MIN: - hw_ctrl->msr_update = update_temporary_min; - break; - case RESCTRL_CTRL_NAME_MAX: - hw_ctrl->msr_update = update_temporary_max; - break; - } - - return true; -} - static __init bool __get_mem_config_intel(struct rdt_resource *r) { struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); - struct resctrl_hw_ctrl *hw_ctrl0, *hw_ctrl1, *hw_ctrl2; + struct resctrl_hw_ctrl *hw_ctrl; union cpuid_0x10_3_eax eax; union cpuid_0x10_x_edx edx; u32 ebx, ecx, max_delay; @@ -234,50 +195,34 @@ static __init bool __get_mem_config_intel(struct rdt_resource *r) if (!(ecx & MBA_IS_LINEAR)) return false; + hw_ctrl = kzalloc_obj(*hw_ctrl); + if (!hw_ctrl) + return false; + + hw_ctrl->r_ctrl.scope = RESCTRL_L3_CACHE; + hw_ctrl->r_ctrl.type = RESCTRL_CTRL_SCALAR; + hw_ctrl->r_ctrl.name = RESCTRL_CTRL_NAME_DEF; + INIT_LIST_HEAD(&hw_ctrl->r_ctrl.domains); + + hw_ctrl->r_ctrl.membw.max_bw = MAX_MBA_BW; + hw_ctrl->r_ctrl.membw.min_bw = MAX_MBA_BW - max_delay; + hw_ctrl->r_ctrl.membw.bw_gran = MAX_MBA_BW - max_delay; + r->bw_delay_linear = true; if (boot_cpu_has(X86_FEATURE_PER_THREAD_MBA)) r->bw_throttle_mode = THREAD_THROTTLE_PER_THREAD; else r->bw_throttle_mode = THREAD_THROTTLE_MAX; - hw_ctrl0 = kzalloc_obj(*hw_ctrl0); - if (!hw_ctrl0) - return false; - - if (!__temporary_multiple_mba_intel_controls(r, hw_ctrl0, ecx, max_delay, RESCTRL_CTRL_NAME_DEF)) { - kfree(hw_ctrl0); - return false; - } - - hw_ctrl1 = kzalloc_obj(*hw_ctrl1); - if (!hw_ctrl1) { - kfree(hw_ctrl0); - return false; - } - - if (!__temporary_multiple_mba_intel_controls(r, hw_ctrl1, ecx, max_delay, RESCTRL_CTRL_NAME_MIN)) { - kfree(hw_ctrl0); - kfree(hw_ctrl1); - return false; - } - - hw_ctrl2 = kzalloc_obj(*hw_ctrl2); - if (!hw_ctrl2) { - kfree(hw_ctrl0); - kfree(hw_ctrl1); - return false; - } + hw_ctrl->r_ctrl.membw.resolution = 100; + hw_ctrl->r_ctrl.membw.tolerance = 5; + hw_ctrl->r_ctrl.membw.scale = 1; + hw_ctrl->r_ctrl.membw.unit = RESCTRL_CTRL_UNIT_ALL; - if (!__temporary_multiple_mba_intel_controls(r, hw_ctrl2, ecx, max_delay, RESCTRL_CTRL_NAME_MAX)) { - kfree(hw_ctrl0); - kfree(hw_ctrl1); - kfree(hw_ctrl2); - return false; - } + hw_ctrl->msr_base = MSR_IA32_MBA_THRTL_BASE; + hw_ctrl->msr_update = mba_wrmsr_intel; + list_add(&hw_ctrl->r_ctrl.entry, &r->controls); - list_add(&hw_ctrl0->r_ctrl.entry, &r->controls); - list_add(&hw_ctrl1->r_ctrl.entry, &r->controls); - list_add(&hw_ctrl2->r_ctrl.entry, &r->controls); r->alloc_capable = true; return true; @@ -434,24 +379,6 @@ static u32 delay_bw_map(unsigned long bw, struct rdt_resource *r) return MAX_MBA_BW; } -static void update_temporary_max(struct msr_param *m) -{ - struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom); - - /* Any control properties available via m->ctrl */ - pr_info("Updata temporary MAX control on domain %d with user value %i\n", - m->dom->hdr.id, hw_dom->ctrl_val[m->low]); -} - -static void update_temporary_min(struct msr_param *m) -{ - struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom); - - /* Any control properties available via m->ctrl */ - pr_info("Updata temporary MIN control on domain %d with user value %i\n", - m->dom->hdr.id, hw_dom->ctrl_val[m->low]); -} - static void mba_wrmsr_intel(struct msr_param *m) { struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom); -- 2.43.0