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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3306061925esm13230568a91.2.2025.09.22.04.28.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 22 Sep 2025 04:28:25 -0700 (PDT) Message-ID: <28eef277-c778-4ffe-94c6-2e90d58633de@oss.qualcomm.com> Date: Mon, 22 Sep 2025 19:28:17 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 12/14] phy: qcom: qmp-usbc: Add QCS615 USB/DP PHY config and DP mode support To: Dmitry Baryshkov Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, li.liu@oss.qualcomm.com, Bjorn Andersson , Konrad Dybcio References: <20250919-add-displayport-support-for-qcs615-platform-v5-0-eae6681f4002@oss.qualcomm.com> <20250919-add-displayport-support-for-qcs615-platform-v5-12-eae6681f4002@oss.qualcomm.com> <14cdf3a4-714c-4136-8c1d-99392e7911f5@oss.qualcomm.com> <2ewxoe76rrii4w3n5b6wl32vmatcp2boj75o65cuq5nx4f2a55@7cn6m7oxzu6c> From: Xiangxu Yin In-Reply-To: <2ewxoe76rrii4w3n5b6wl32vmatcp2boj75o65cuq5nx4f2a55@7cn6m7oxzu6c> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: 1fiy02Y52TsSGsIG0donx85j2BwkeBr- X-Authority-Analysis: v=2.4 cv=RO2zH5i+ c=1 sm=1 tr=0 ts=68d132dc cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=XVeZa78dugChcG7OFuEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIwMDAyNSBTYWx0ZWRfX4041oYGW2nww x3QU3EXhZ8V6/BNFN53wGdu7Mp23mj2CI0LbSRDEtu2EZVltP2GIYDIBqnO+SEacwaNCldqRpcD lYOS9XU/5uxP3ZPmJrzL5wAJO0IS0t2TrZh9Bh/kgXLSZ6Nc6ydtuwlFOSZKPwfDmTwmxLzAFLq depXifz37liaEjb+WMdibHTGBrIr4EQAsVcyIGJTVYPccgiWXRzgEgiTpTlkQZAuKdwkyNZPq5f PfVeBoE4pUzd+eJG2P06Zfe27h2ZLsIoPGf7MbYLlmJBvniPbaNjPbRjkHsc7LcRU+mXqLXKK3x 6rdUVAOzttUN/Rc+LJlywgjBDVesn2+53McQJSM7TXac/k7mSZG0btL9UHP6Obbv3sbQAdyoQZ3 8+tcBCvr X-Proofpoint-ORIG-GUID: 1fiy02Y52TsSGsIG0donx85j2BwkeBr- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-22_01,2025-09-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 suspectscore=0 priorityscore=1501 impostorscore=0 spamscore=0 adultscore=0 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509200025 On 9/22/2025 5:45 PM, Dmitry Baryshkov wrote: > On Mon, Sep 22, 2025 at 02:58:17PM +0800, Xiangxu Yin wrote: >> On 9/20/2025 2:41 AM, Dmitry Baryshkov wrote: >>> On Fri, Sep 19, 2025 at 10:24:29PM +0800, Xiangxu Yin wrote: >>>> Add QCS615-specific configuration for USB/DP PHY, including DP init >>>> routines, voltage swing tables, and platform data. Add compatible >>>> "qcs615-qmp-usb3-dp-phy". >>>> >>>> Signed-off-by: Xiangxu Yin >>>> --- >>>> drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 395 +++++++++++++++++++++++++++++++ >>>> 1 file changed, 395 insertions(+) >>>> >>>> + >>>> + writel(0x3f, qmp->dp_tx + QSERDES_V2_TX_TRANSCEIVER_BIAS_EN); >>>> + writel(0x10, qmp->dp_tx + QSERDES_V2_TX_HIGHZ_DRVR_EN); >>>> + writel(0x0a, qmp->dp_tx + QSERDES_V2_TX_TX_POL_INV); >>>> + writel(0x3f, qmp->dp_tx2 + QSERDES_V2_TX_TRANSCEIVER_BIAS_EN); >>>> + writel(0x10, qmp->dp_tx2 + QSERDES_V2_TX_HIGHZ_DRVR_EN); >>>> + writel(0x0a, qmp->dp_tx2 + QSERDES_V2_TX_TX_POL_INV); >>> Are you sure that these don't need to be adjusted based on >>> qmp->orientation or selected lanes count? >>> >>> In fact... I don't see orientation handling for DP at all. Don't we need >>> it? >> >> Thanks for the review. >> >> I agree with your reasoning and compared talos 14nm HPG with hana/kona >> 7nm PHY HPG; the 7nm COMBO PHY series has orientation/lane-count dependent >> configs, but the 14nm PHY series does not. On QCS615 (talos), the TX_* >> registers you pointed to are programmed with constant values regardless >> of orientation or lane count. This has been confirmed from both the HPG >> and the downstream reference driver. > Thanks for the confirmation. > >> For orientation, from reference the only difference is DP_PHY_MODE, which >> is set by qmp_usbc_configure_dp_mode(). The DP PHY does have an >> SW_PORTSELECT-related register, but due to talos lane mapping from the >> DP controller to the PHY not being the standard <0 1 2 3> sequence, it >> cannot reliably handle orientation flip. Also, QCS615 is a fixed- >> orientation platform (not DP-over-TypeC), so there is no validated hardware >> path for orientation flip on this platform. > Wait... I thought that the the non-standard lane order is handled by the > DP driver, then we should be able to handle the orientation inside PHY > driver as usual. Yes, I have confirmed this with our verification team. For the non-standard lane order, handling flip requires swapping mapped  lane 0 ↔ lane 3 and lane 1 ↔ lane 2 in the logical2physical mapping. This is a hardware limitation, and with the current PHY driver we cannot propagate orientation status to dp_ctrl for processing. > Anyway, please add a FIXME comment into the source file and a note to > the commit message that SW_PORTSELECT should be handled, but it's not a > part of this patch for the stated reasons. OK, I will add a |FIXME| comment in |qmp_usbc_dp_power_on| and update the related commit message. >> >>>> + >>>> + writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); >>>> + writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); >>>> + >>>> + if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V2_DP_PHY_STATUS, >>>> + status, >>>> + ((status & BIT(1)) > 0), >>>> + 500, >>>> + 10000)){ >>>> + dev_err(qmp->dev, "PHY_READY not ready\n"); >>>> + return -ETIMEDOUT; >>>> + } >>>> + >>>> + return 0; >>>> +} >>>> +