From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753007AbcHQMkX (ORCPT ); Wed, 17 Aug 2016 08:40:23 -0400 Received: from foss.arm.com ([217.140.101.70]:52711 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751839AbcHQMkW (ORCPT ); Wed, 17 Aug 2016 08:40:22 -0400 Subject: Re: [PATCH] irqchip/gicv3: remove disabling redistributor and group1 non-secure interrupts To: Christopher Covington , linux-kernel@vger.kernel.org References: <1471342766-18445-1-git-send-email-sudeep.holla@arm.com> <6ae5bf2a-22b2-54a7-c576-ce86ad347c60@codeaurora.org> Cc: Sudeep Holla , Thomas Gleixner , Jason Cooper , Marc Zyngier , Lorenzo Pieralisi , Prashanth Prakash From: Sudeep Holla Organization: ARM Message-ID: <29104bbe-d5ea-3f48-d75b-f0863b64d28d@arm.com> Date: Wed, 17 Aug 2016 13:39:10 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: <6ae5bf2a-22b2-54a7-c576-ce86ad347c60@codeaurora.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Christopher, On 16/08/16 20:21, Christopher Covington wrote: > Thanks Sudeep! > > On 08/16/2016 06:19 AM, Sudeep Holla wrote: >> As per the GICv3 specification, to power down a processor using GICv3 >> and allow automatic power-on if an interrupt must be sent to a processor, >> software must set Enable to zero for all interrupt groups(by writing >> to GICC_CTLR or ICC_IGRPEN{0,1}_EL1/3 as appropriate. >> >> When commit 3708d52fc6bb ("irqchip: gic-v3: Implement CPU PM notifier") >> was introduced there were no firmware implementations(in particular PSCI) >> handling this. >> >> Linux kernel may not be aware of the CPU power state details and might >> fail to identify the power states that require quiescing the CPU >> interface. Even if it can be aware of those details, it can't determine >> which CPU power state have been triggered at the platform level and how >> the power control is implemented. >> >> This patch make disabling redistributor and group1 non-secure interrupts >> in the power down path and re-enabling of redistributor in the power-up >> path conditional. It will be handled in the kernel if and only if the >> non-secure accesses are permitted to access and modify control registers. >> It is left to the platform implementation otherwise. >> >> Cc: Marc Zyngier >> Cc: Lorenzo Pieralisi >> Signed-off-by: Sudeep Holla >> --- >> drivers/irqchip/irq-gic-v3.c | 11 +++++++++-- >> 1 file changed, 9 insertions(+), 2 deletions(-) >> >> Hi Christopher, >> >> Can you check if ACPI processor idle works with this patch on QDF2432 ? > > This fixes the boot hang, and I see the usage and time files in cpuidle > sysfs increasing on an idle system. > > Tested-by: Christopher Covington > Thanks for testing. I found the when CPU_PM is disabled, build triggers a warning. I will move gic_dist_security_disabled inside the ifdef CPU_PM and post v2. -- Regards, Sudeep