From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.4 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70758C00A89 for ; Mon, 2 Nov 2020 16:07:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2B5A122268 for ; Mon, 2 Nov 2020 16:07:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="M1egA/6R" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726871AbgKBQEr (ORCPT ); Mon, 2 Nov 2020 11:04:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726854AbgKBQEn (ORCPT ); Mon, 2 Nov 2020 11:04:43 -0500 Received: from mail-qv1-xf49.google.com (mail-qv1-xf49.google.com [IPv6:2607:f8b0:4864:20::f49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD1E4C0617A6 for ; Mon, 2 Nov 2020 08:04:41 -0800 (PST) Received: by mail-qv1-xf49.google.com with SMTP id o12so1309244qvw.1 for ; Mon, 02 Nov 2020 08:04:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:date:in-reply-to:message-id:mime-version:references:subject :from:to:cc; bh=VsN8c2WI1TMox3v/PYtKI3bTw78pIVnf1hcHZhXvdoM=; b=M1egA/6RbV9qQ9SDV7wZ1UNoR8Pff1wFC083SCkcQKfnsgv5twQ9bSOeF6rIAyg+q2 yuRY0m5AolHyr8nnEh+8NBFAlt7ssj5pWCjb17HiDGHQxVxtN9OlrnZjUgDY53yVfPcw rskl85yGKC+v3r+N0dWw0FqRblNFA/7CsbHI237wQCKQVCdVZ8kLSDeqxxrZr1NdenZa Fk0bFuqEvsrq30pbklqr+tiub1M6DMTGkEqrRFYmTl0hsKMi7H3odK3d6/d+eVcOavSk hcSt21DIUaZFd4YwaEmnFxqFbh0YF6mVD/aWO9zkZ9j90K1Nns2c0YbHw+/32lkoDI5V UDhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=VsN8c2WI1TMox3v/PYtKI3bTw78pIVnf1hcHZhXvdoM=; b=rMuqGd2kIcY/HWUVJLPNkWYI7R4hmvqDCujm5fWmTE6R80W2kzVdjsqqM3OTVFsm95 orPWmmhhMk3R35NP5X9TN4+9wdRke7T4zPQRsSdOprBbP4eS0HOA2z/K5TiR2cJyRA0j RXzRVMIDpLGKBalhxy4JTnU3541IVolo8SUvvMfgW4fB1P5foT5EgaaP4ta3N0xaQK4x 8aIWVmwmwVQ43S45jRFkO3HCSUiLrHWRw/+6+KfUxy9vXipS9X6XLtCMAF3XUOWRT6/S 40Xt5R+mYVbEUKp87JfWJyjgmjxzKtaoUaZOrXBp7K/HSvmhgTvLiVYN6Za9j09/fKd+ WBfQ== X-Gm-Message-State: AOAM530sdVQL3vxvsxnnD46yU95B/xMoOxrEYBPU6bzusZ1+E9Sp5nx2 U4Ty6uCAgYvAhGi++pLCAPGrSUmHsUwX31GT X-Google-Smtp-Source: ABdhPJwRjdkGZcpAEGzSh4QMc5CdQQ+dmOJxKegYoZaSvVJf05B349Ft5a4YLWBwLaS6ou5tXYI8GpFINX8AdZHL Sender: "andreyknvl via sendgmr" X-Received: from andreyknvl3.muc.corp.google.com ([2a00:79e0:15:13:7220:84ff:fe09:7e9d]) (user=andreyknvl job=sendgmr) by 2002:a0c:baa2:: with SMTP id x34mr22633076qvf.23.1604333081018; Mon, 02 Nov 2020 08:04:41 -0800 (PST) Date: Mon, 2 Nov 2020 17:03:46 +0100 In-Reply-To: Message-Id: <29259e315987b3cff3c6bf2ebac9cc089b7413a0.1604333009.git.andreyknvl@google.com> Mime-Version: 1.0 References: X-Mailer: git-send-email 2.29.1.341.ge80a0c044ae-goog Subject: [PATCH v7 06/41] arm64: kasan: Enable in-kernel MTE From: Andrey Konovalov To: Catalin Marinas , Will Deacon Cc: Vincenzo Frascino , kasan-dev@googlegroups.com, Dmitry Vyukov , Andrey Ryabinin , Alexander Potapenko , Marco Elver , Evgenii Stepanov , Elena Petrova , Branislav Rankov , Kevin Brodsky , Andrew Morton , linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, Andrey Konovalov Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Vincenzo Frascino Hardware tag-based KASAN relies on Memory Tagging Extension (MTE) feature and requires it to be enabled. The Tag Checking operation causes a synchronous data abort as a consequence of a tag check fault when MTE is configured in synchronous mode. Enable MTE in Synchronous mode in EL1 to provide a more immediate way of tag check failure detection in the kernel. As part of this change enable match-all tag for EL1 to allow the kernel to access user pages without faulting. This is required because the kernel does not have knowledge of the tags set by the user in a page. Note: For MTE, the TCF bit field in SCTLR_EL1 affects only EL1 in a similar way as TCF0 affects EL0. MTE that is built on top of the Top Byte Ignore (TBI) feature hence we enable it as part of this patch as well. Signed-off-by: Vincenzo Frascino Signed-off-by: Andrey Konovalov Reviewed-by: Catalin Marinas --- Change-Id: I4d67497268bb7f0c2fc5dcacefa1e273df4af71d --- arch/arm64/kernel/cpufeature.c | 7 +++++++ arch/arm64/mm/proc.S | 23 ++++++++++++++++++++--- 2 files changed, 27 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index dcc165b3fc04..c61f201042b2 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1704,6 +1704,13 @@ static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) cleared_zero_page = true; mte_clear_page_tags(lm_alias(empty_zero_page)); } + + /* Enable in-kernel MTE only if KASAN_HW_TAGS is enabled */ + if (IS_ENABLED(CONFIG_KASAN_HW_TAGS)) { + /* Enable MTE Sync Mode for EL1 */ + sysreg_clear_set(sctlr_el1, SCTLR_ELx_TCF_MASK, SCTLR_ELx_TCF_SYNC); + isb(); + } } #endif /* CONFIG_ARM64_MTE */ diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 23c326a06b2d..7c3304fb15d9 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -40,9 +40,15 @@ #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA #ifdef CONFIG_KASAN_SW_TAGS -#define TCR_KASAN_FLAGS TCR_TBI1 +#define TCR_KASAN_SW_FLAGS TCR_TBI1 #else -#define TCR_KASAN_FLAGS 0 +#define TCR_KASAN_SW_FLAGS 0 +#endif + +#ifdef CONFIG_KASAN_HW_TAGS +#define TCR_KASAN_HW_FLAGS SYS_TCR_EL1_TCMA1 | TCR_TBI1 +#else +#define TCR_KASAN_HW_FLAGS 0 #endif /* @@ -427,6 +433,10 @@ SYM_FUNC_START(__cpu_setup) */ mov_q x5, MAIR_EL1_SET #ifdef CONFIG_ARM64_MTE + mte_tcr .req x20 + + mov mte_tcr, #0 + /* * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported * (ID_AA64PFR1_EL1[11:8] > 1). @@ -447,6 +457,9 @@ SYM_FUNC_START(__cpu_setup) /* clear any pending tag check faults in TFSR*_EL1 */ msr_s SYS_TFSR_EL1, xzr msr_s SYS_TFSRE0_EL1, xzr + + /* set the TCR_EL1 bits */ + mov_q mte_tcr, TCR_KASAN_HW_FLAGS 1: #endif msr mair_el1, x5 @@ -456,7 +469,11 @@ SYM_FUNC_START(__cpu_setup) */ mov_q x10, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \ - TCR_TBI0 | TCR_A1 | TCR_KASAN_FLAGS + TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS +#ifdef CONFIG_ARM64_MTE + orr x10, x10, mte_tcr + .unreq mte_tcr +#endif tcr_clear_errata_bits x10, x9, x5 #ifdef CONFIG_ARM64_VA_BITS_52 -- 2.29.1.341.ge80a0c044ae-goog