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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-634a3b05bafsm975284a12.53.2025.09.25.03.16.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Sep 2025 03:16:30 -0700 (PDT) Message-ID: <2960a6fc-106b-4280-b4d4-9c1a3a449454@oss.qualcomm.com> Date: Thu, 25 Sep 2025 12:16:28 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts To: Pankaj Patil , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250925-v3_glymur_introduction-v1-0-24b601bbecc0@oss.qualcomm.com> <20250925-v3_glymur_introduction-v1-3-24b601bbecc0@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250925-v3_glymur_introduction-v1-3-24b601bbecc0@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: QIjWrxvvAy3w7vV4Z6l8W2ywsZHaN9Tv X-Authority-Analysis: v=2.4 cv=YMOfyQGx c=1 sm=1 tr=0 ts=68d51681 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=h9bIO8qCkgbVbkUqMQIA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIwMDAwNCBTYWx0ZWRfX07hun3OkpYIG eWaL/NiFbgivXNigewVZzbKTNlG2EWI7oqeKbQm2RAHFmKdOIk9b1WOqsFvX00upS8Q3oc81tAR oxKyWoryeLPPmKNNWkEmoV8lfLOBnxzgiyETrox3D+eP/p4X0YPsW8oNnNrA7AjXuRP2svSZXmP l4xoxe9Cb9gAyJNCsMlLda0TqNCiIvjnJTlzLovxhzWP5dsdhxBcJum2e/1voj4KIU936AFDttU +J0ExpRJ5yWV5qhOhrPAeInnl1IhRA0XhkBJhYJoPOINYme65KKVVHeorvetTCH0FbSLIYb6Nsv opIbF9uc0sG4E4hjwov+of5eqsiBfYUen1PwKyWjJXzqzkNk+80HTPQWCvJ1GpErB9GJaVpzyxL ths/pj8F X-Proofpoint-ORIG-GUID: QIjWrxvvAy3w7vV4Z6l8W2ywsZHaN9Tv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-24_07,2025-09-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 adultscore=0 priorityscore=1501 spamscore=0 clxscore=1015 suspectscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509200004 On 9/25/25 8:32 AM, Pankaj Patil wrote: > Introduce initial device tree support for Glymur - Qualcomm's > next-generation compute SoC and it's associated Compute Reference > Device (CRD) platform. > > The dt describes CPUs, CPU map, GCC and RPMHCC clock controllers, > geni UART, interrupt controller, TLMM, reserved memory, > interconnects, SMMU, firmware scm, watchdog, apps rsc, RPMHPD, > SRAM, PSCI and pmu nodes. > > Signed-off-by: Pankaj Patil > --- [...] > +#include "glymur.dtsi" > + > +/ { > + model = "Qualcomm Technologies, Inc. Glymur CRD"; > + compatible = "qcom,glymur-crd", "qcom,glymur"; > + > + aliases { > + serial0 = &uart21; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +&tlmm { > + gpio-reserved-ranges = <4 4>, <10 2>, <44 4>; /*Security SPI (TPM)*/ Please add a space between the comment begin/end markers and the content > +}; > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi > new file mode 100644 > index 0000000000000000000000000000000000000000..f1c5a0cb483670e9f8044e250950693b4a015479 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi > @@ -0,0 +1,1320 @@ > +// SPDX-License-Identifier: GPL-2.0-only This is different.. [...] > + cpu0: cpu0@0 { "cpu@" > + device_type = "cpu"; > + compatible = "qcom,oryon"; We've beaten this horse to death, over and over again. This compatible is meaningless, incorrect and shall not be merged [...] > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { Please ensure a \n between subsequent subnodes [...] > + soc: soc@0 { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; compatible goes first [...] > + tcsrcc: clock-controller@1fd5044 { > + compatible = "qcom,glymur-tcsr"; > + reg = <0x0 0x1fd5044 0x0 0x48>; We can map 0x1fd5000 - 0x1fd5094 inclusive, as that seems like a logical subblock (this would require adjusting the driver) There's also a laaaarge pool of various TCSR_ registers between the previous node and this one.. but we can leave that in case we need to describe it in a specific way some day > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + tcsr: syscon@1fd6000 { > + compatible = "syscon"; "syscon" alone was not allowed by the dt checker at one point.. > + reg = <0x0 0x1fd6000 0x0 0x20000>; > + }; [...] > + frame@17811000 { > + reg = <0x0 0x17811000 0x0 0x1000>, > + <0x0 0x17812000 0x0 0x1000>; Odd spacing (more than 1 space after '=') Konrad