From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78DADC6FA82 for ; Thu, 15 Sep 2022 01:24:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229994AbiIOBYv (ORCPT ); Wed, 14 Sep 2022 21:24:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229863AbiIOBYr (ORCPT ); Wed, 14 Sep 2022 21:24:47 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 003A211C00; Wed, 14 Sep 2022 18:24:41 -0700 (PDT) X-UUID: 1153459182e441fea09a3acc01c11218-20220915 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=yWiqkRoMA5szwFch3bndA/3HuivLlnD9Nl9WlTv4YVY=; b=Uuk3FPlR4i6kGpKTRIvihshdQ380JsGYWGpMHTStL/y7BeP1jpQlR1RPqfUbmPE5SqkWT0AUr7A6ujOSWwe82gCr0+se02SGn6LSESZDkSp5mnJoz3Z91rLt9ydV24UecZSo2tL0rd8o4Tnk9fHIx5PWzhmQGRZYACqQtDUruGY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:e68d4a5b-f68b-4f1e-b6d5-cba8538f273f,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:39a5ff1,CLOUDID:ac896ff6-6e85-48d9-afd8-0504bbfe04cb,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 1153459182e441fea09a3acc01c11218-20220915 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1828666474; Thu, 15 Sep 2022 09:24:32 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 15 Sep 2022 09:24:31 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 15 Sep 2022 09:24:31 +0800 Message-ID: <296155e2a12a474439ba092e73b4bcffbf3d3edc.camel@mediatek.com> Subject: Re: [PATCH 1/5] dt-bindings: arm: mediatek: mmsys: change compatible for MT8195 From: Jason-JH Lin To: Matthias Brugger , Chun-Kuang Hu , Rob Herring , "Krzysztof Kozlowski" , AngeloGioacchino Del Regno CC: CK Hu , Rex-BC Chen , "Singo Chang" , Nancy Lin , , , , , , Date: Thu, 15 Sep 2022 09:24:31 +0800 In-Reply-To: <1b739216-8bb1-162b-1af5-24acba7324bf@gmail.com> References: <20220914182331.20515-1-jason-jh.lin@mediatek.com> <20220914182331.20515-2-jason-jh.lin@mediatek.com> <1b739216-8bb1-162b-1af5-24acba7324bf@gmail.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Matthias, Thanks for the reviews. On Wed, 2022-09-14 at 23:24 +0200, Matthias Brugger wrote: > > On 14/09/2022 20:23, Jason-JH.Lin wrote: > > For previous MediaTek SoCs, such as MT8173, there are 2 display HW > > pipelines binding to 1 mmsys with the same power domain, the same > > clock driver and the same mediatek-drm driver. > > > > For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding > > to > > 2 different power domains, different clock drivers and different > > mediatek-drm drivers. > > > > Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR, > > CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture > > Quality) > > and they makes VDOSYS0 supports PQ function while they are not > > including in VDOSYS1. > > > > Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related > > component). It makes VDOSYS1 supports the HDR function while it's > > not > > including in VDOSYS0. > > > > To summarize0: > > Only VDOSYS0 can support PQ adjustment. > > Only VDOSYS1 can support HDR adjustment. > > > > Therefore, we need to separate these two different mmsys hardwares > > to > > 2 different compatibles for MT8195. > > > > Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195 > > SoC binding") > > Signed-off-by: Jason-JH.Lin > > Signed-off-by: Bo-Chen Chen > > Acked-by: Krzysztof Kozlowski > > I'm not sure Krzysztof gave his Acked-by tag. I'll remove this tag. > > > --- > > .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | > > 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam > > l > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam > > l > > index 6ad023eec193..a53b32c0a608 100644 > > --- > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam > > l > > +++ > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam > > l > > @@ -32,6 +32,8 @@ properties: > > - mediatek,mt8186-mmsys > > - mediatek,mt8192-mmsys > > - mediatek,mt8195-mmsys > > + - mediatek,mt8195-vdosys0 > > As I said in the last submission, we should make mediatek,mt8195- > mmsys as a > fallback of vdosys0. Actually mediatek,mt8195-mmsys is only used for > the > fallback of vdosys0. I think adding both vdosys0 and vdosys1 can make the description of this patch clearer. It's find to me to only add "mediatek,mt8195-vdosys0" in this patch. So I'll remove the "mediatek,mt8195-vdosys1" at the next version. Regards, Jason-JH.Lin > > Regards, > Matthias > > > + - mediatek,mt8195-vdosys1 > > - mediatek,mt8365-mmsys > > - const: syscon > > - items: > > -- Jason-JH Lin