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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-adec8158d33sm356206366b.31.2025.06.14.12.59.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 14 Jun 2025 12:59:16 -0700 (PDT) Message-ID: <296a9ab8-04e3-4623-8246-c8fd3fca8d98@oss.qualcomm.com> Date: Sat, 14 Jun 2025 21:59:13 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 5/5] phy: qcom: qmp-pcie: add x1e80100 qref supplies To: Johan Hovold , Wenbin Yao Cc: catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, kishon@kernel.org, sfr@canb.auug.org.au, linux-phy@lists.infradead.org, krishna.chundru@oss.qualcomm.com, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_cang@quicinc.com, qiang.yu@oss.qualcomm.com, Johan Hovold , Abel Vesa References: <20250604080237.494014-1-quic_wenbyao@quicinc.com> <20250604080237.494014-6-quic_wenbyao@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: 6KVw1zbTXb24b7pK3tt137rxBpll7pF0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjE0MDE2NiBTYWx0ZWRfXyBGkU4XdTKlZ HggdnleTTqVa5sQutTneixaT6DcteoJCOgKI1/ZMqMfADUdUDdrbRQuxXDiTLYbwHgsJqevCPhu QDYn+K3piDMNYhFBBDCPdMNvdFxzuPTL2ySRap6H/fA+cxjZa3h6B9WjJ2qMj6PtuPphSO9X5pf XCynhyOi9I751tq7xjLr6IrVNUqNOdQTTJVzvNF7MQziCwS+1V0gT2I9o0iA9dV8sGo1Z+MgApp bHKfRTpJJVEG47WFBnxeV/2d28MFta7RI8LyMigNZZA3orlJlBSvJbZcwZFIGHk/D5RFI1J8HWW k8Zi1jDbW+9Av8giGAAquICwFG4miAcpqgYeYRBiIR7Dgo5XBmk0W5XYEC3VEnawC+zXi7G2/YC bJTIm6oaAW4DiHOG5luOPUJfWhxQuhdd3Quasev+B+zda+SMr0tKki0RdhpRySmcyD0Ra/XS X-Authority-Analysis: v=2.4 cv=UL/dHDfy c=1 sm=1 tr=0 ts=684dd496 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=VwQbUJbxAAAA:8 a=zitRP-D0AAAA:8 a=EUspDBNiAAAA:8 a=6rhPmxELWQzppWOSQc8A:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 a=xwnAI6pc5liRhupp6brZ:22 X-Proofpoint-GUID: 6KVw1zbTXb24b7pK3tt137rxBpll7pF0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-14_08,2025-06-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 phishscore=0 mlxlogscore=999 malwarescore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506140166 On 6/4/25 5:10 PM, Johan Hovold wrote: > On Wed, Jun 04, 2025 at 04:02:37PM +0800, Wenbin Yao wrote: >> From: Qiang Yu >> >> All PCIe PHYs on the X1E80100 SOC require the vdda-qref, which feeds QREF >> clocks provided by the TCSR device. > > As I just mentioned in the thread where this is still being discussed: > > https://lore.kernel.org/all/aEBfV2M-ZqDF7aRz@hovoldconsulting.com > > you need to provide a lot more detail on why you think modelling these > supplies as PHY supplies (which they are not) is the right thing to do. > > Also please answer the question I've asked three times now on how the > QREF supplies map to PHY supplies on X1E as no one will be able to use > this binding unless this is documented somewhere (and similar for other > SoCs). > > The fact that you so far have not been able to provide an answer > seems to suggest that these supplies need to be managed by the TCSR > clock driver which can handle the mapping. To emphasize, we apparently can't do it, because there exist IPs where the QREF *ref clock* is not expressed through a bit in TCSR (which we interpret as TCSR_CC), but the *supply* for that clock must still be described somehow, as it obviously needs power. To add to the mess, it may be that there is more than one supply per reference clock required (which is not necessarily an issue when the driver takes care of it, but something to keep in mind). Konrad