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Wed, 07 Oct 2026 04:00:21 -0700 (PDT) X-Received: by 2002:a17:90b:5887:b0:3a7:250:386e with SMTP id 98e67ed59e1d1-3a8a07404admr1701772a91.22.1791370821390; Wed, 07 Oct 2026 04:00:21 -0700 (PDT) Received: from [10.217.216.105] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cd0a92d5ebesm1232959a12.12.2026.10.07.04.00.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 07 Oct 2026 04:00:20 -0700 (PDT) Message-ID: <297690cb-64d8-4e7d-9d97-66680f6a2b99@oss.qualcomm.com> Date: Wed, 7 Oct 2026 16:30:12 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/5] arm64: dts: qcom: glymur: Add UFS nodes To: Dmitry Baryshkov Cc: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Avri Altman , Bart Van Assche , Bjorn Andersson , Konrad Dybcio , gopikrishna.garmidi@oss.qualcomm.com, jagadeesh.kona@oss.qualcomm.com, Abel Vesa , Abel Vesa , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, nitin.rawat@oss.qualcomm.com, sibi.sankar@oss.qualcomm.com, Taniya Das References: <20261007-glymur_ufs_qcb_enablement-v3-0-84cf4f861415@oss.qualcomm.com> <20261007-glymur_ufs_qcb_enablement-v3-3-84cf4f861415@oss.qualcomm.com> Content-Language: en-US From: Pradeep Pragallapati In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: TFkyq5X5UDpezdsGJCev-nOrOyW312IQ X-Authority-Analysis: v=2.4 cv=ZZiIpcVA c=1 sm=1 tr=0 ts=6ac62647 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=SwwKY9vyf4oML-p5yksA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA3MDA0MyBTYWx0ZWRfX0TPdYG1fCsOs +SskQh0AIrOTioPNizB/IicRIGElx3REYNl7nwzJE1o1Mb6kOBlQH6ZWCE29fNqNfi6PLJp9uam rdulCyfLFfYMxGrfyoTofbLk3k1D09U= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA3MDA0MyBTYWx0ZWRfX5EYE4Wxv+Odh uwMP1V0b3sM0aNolrDkc5sN8cT64bcoMRjUDPIMwe3HplNih32vkVeecDHMDoP5V9bSb8INGuDR Xmki1KmW54agUGjAEYY8sgs3N+1IIyPgl6NOtSe19YQFBNE40KWoM2qcpICsgpQD3zvMXEoxgPH OCTF5EJ+ItXnofcTC/b4CYMNQ2wMesoDgdIxMIjiDauc+7vcPfw4nHd2U5613ZIzj2DXGJRZ4zN S5aVvxekG+ENTavz08PmF6sQjtGUo61RCa07rKUAgWQJbH2CW48M6NeluaYaLZAM0MnGGEKdmmG lCY++Ir1AoK2t5PfcT3EDWZ+oF+J/QRTetGzL2w2XontSfVUak5oD9YlLmoZPtDLmFY9DxnCCoN fz0coAh2Q/qpoTt4tqJIkuzZzLjAVr8aAy+3Ru3irlSUlQHSVebs57C7QK1VI4yQf3Ar/IcyY4e P160abWJP7gJJsBlNhg== X-Proofpoint-ORIG-GUID: TFkyq5X5UDpezdsGJCev-nOrOyW312IQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-07_03,2026-10-06_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610070043 On 10/7/2026 1:13 PM, Dmitry Baryshkov wrote: > On Wed, Oct 07, 2026 at 11:59:36AM +0530, Pradeep P V K wrote: >> Add UFS PHY and UFS host controller nodes for Glymur SoC. >> >> Reviewed-by: Abel Vesa >> Signed-off-by: Pradeep P V K >> --- >> arch/arm64/boot/dts/qcom/glymur.dtsi | 125 ++++++++++++++++++++++++++++++++++- >> 1 file changed, 122 insertions(+), 3 deletions(-) >> >> @@ -4102,6 +4102,125 @@ rng: rng@10c3000 { >> reg = <0x0 0x010c3000 0x0 0x1000>; >> }; >> >> + ufs_mem_phy: phy@1d80000 { >> + compatible = "qcom,glymur-qmp-ufs-phy"; >> + reg = <0x0 0x01d80000 0x0 0x2000>; >> + >> + clocks = <&rpmhcc RPMH_CXO_CLK>, >> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, >> + /* UFS and PCIE4 share the same clkref */ >> + <&tcsr TCSR_PCIE_4_CLKREF_EN>; >> + >> + clock-names = "ref", >> + "ref_aux", >> + "qref"; >> + >> + resets = <&ufs_mem_hc 0>; >> + reset-names = "ufsphy"; > > power-domains = <&gcc GCC_UFS_PHY_GDSC> ? Or is there > GCC_UFS_MEM_PHY_GDSC, which is simply not described in gcc? > > If there are none, it should be reflected in the DT bindings, together > with the explanation in the commit message. > Yes, Glymur SoC does not support UFS PHY GDSC. Sure, i will update the DT-bindings accordingly and include the explanation in the commit of next patch series. >> + >> + #clock-cells = <1>; >> + #phy-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >