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Wed, 17 Jun 2026 02:30:43 -0700 (PDT) X-Received: by 2002:a05:620a:438b:b0:8f1:9e59:2208 with SMTP id af79cd13be357-91d8acdc8f3mr299012085a.4.1781688643022; Wed, 17 Jun 2026 02:30:43 -0700 (PDT) Received: from [192.168.120.170] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bfdb4b22136sm788125566b.15.2026.06.17.02.30.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Jun 2026 02:30:42 -0700 (PDT) Message-ID: <29806448-0588-4590-8540-a689ccf1e7b0@oss.qualcomm.com> Date: Wed, 17 Jun 2026 11:30:39 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] input: misc: Add Qualcomm SPMI PMIC haptics driver To: Fenglin Wu , linux-arm-msm@vger.kernel.org, Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Stephen Boyd , Bjorn Andersson , Konrad Dybcio Cc: David Collins , Subbaraman Narayanamurthy , Kamal Wadhwa , kernel@oss.qualcomm.com, linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260616-qcom-spmi-haptics-v1-0-d24e422de6b4@oss.qualcomm.com> <20260616-qcom-spmi-haptics-v1-3-d24e422de6b4@oss.qualcomm.com> <1bcf00ae-2558-4c3a-970d-aee1da0c06f9@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <1bcf00ae-2558-4c3a-970d-aee1da0c06f9@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: cXJbGMFhJphbwBShVMF1fYWj0RL6KoQF X-Authority-Analysis: v=2.4 cv=JufBas4C c=1 sm=1 tr=0 ts=6a326944 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=IsPFB7xf8fGKp3IZfZcA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-ORIG-GUID: cXJbGMFhJphbwBShVMF1fYWj0RL6KoQF X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE3MDA4OSBTYWx0ZWRfX76zqckTFsvLq ybqowjZquK2YRJyFvUHalfP4Hc9B/4s5Jx/AI8AmmgUBk6DR6F0eQ+NVOrM+Iiif+AqYTz6XJ3j io5UieXv9Qru51S5OQjRIjBEJ+KTQf0hGKdEEj6oMyhYDn7KAvTHTNE4XvvXcH5E4YiZEh6h41w D4akzCLkhO6bIMTjRozcaq0TBLQ0R69sHwa/SoW0kNUkYRgCbZVUxh5vB0g+hG0da/WQsuIqW07 lJl20iX9HDat+k007eosa8vThYHhZZxfk2/qIb4BIETYzeoWWm1ts/vZErLVUaULhEQrSoTvjxM l3LpTI95WgdKYUPumCWWpswZ7jVNZoTiHtcqmsnKKN1o8pFcwD0z3w3OB/rgWjxkxj9flMAKDuv bbvu9Xlgrzq3eKYjY9daAKihxANimafvU4vDie8f55Kwm2nWOm+4XgUrF0AGi6yE7LJV9FMF6GD EaZMe2NTabiOvwKI3VA== X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE3MDA4OSBTYWx0ZWRfXzdl1+iGkRAeD 6sfzpD1jUau5gxQW/xE/Fwj3baFBEkmAwC6UrGP95U6y851au6JXqvmM8y4Fj/tPTCq7Z6fcezQ WzTKJ5oBSVzyyR4ljVBf9cB+6iByPuo= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-17_01,2026-06-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 adultscore=0 priorityscore=1501 impostorscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606170089 On 6/17/26 4:31 AM, Fenglin Wu wrote: >>> +        ret = ptn_bulk_write(h, HAP_PTN_FIFO_DIN_0_REG, &data[i], 4); >>> +        if (ret) >>> +            return ret; >>> +    } >>> + >>> +    for (; i < len; i++) { >>> +        ret = ptn_write(h, HAP_PTN_FIFO_DIN_1B_REG, (u8)data[i]); >>> +        if (ret) >>> +            return ret; >>> +    } >> So if i'm reading this right, the first loop will always write >> 4*(len//4) bytes and the second one will be entered at most once, >> to write len rem 4 bytes.. should this be an if instead? > > I should put a comment for clarification. Here’s some background: FIFO data writing supports both 4-byte bulk writes using registers [HAP_PTN_FIFO_DIN_0_REG ... HAP_PTN_FIFO_DIN_3_REG], and 1-byte writes using the HAP_PTN_FIFO_DIN_1B_REG register. The 4-byte bulk write is more efficient, especially for waveform which has several Kb data, and it helps to reduce software latency when loading effects and reduce the delay in triggering vibration. It also helps prevent the FIFO from running dry during data refill in FIFO-empty interrupts. Typically, we use 4-byte writes for the initial 4-byte aligned data, and 1-byte writes for any trailing remainder. > > So it still needs a 'for' loop here since the remainder could be more than 1 byte. Right, I mentioned len rem 4 but failed to notice it's a single-byte write.. anyway, a comment here would be good > >>> + >>> +    return 0; >>> +} >>> + >>> +/* >>> + * Configure the hardware FIFO memory boundary. >>> + * FIFO occupies addresses [0, fifo_len). >>> + */ >>> +static int haptics_configure_fifo_mmap(struct qcom_haptics *h) >>> +{ >>> +    u32 fifo_len, fifo_units; >>> + >>> +    /* Config all memory space for FIFO usage for now */ >> What's the not-"for now" endgame for this? > > The hardware supports more modes than the two currently supported in the driver. One of these, called 'PAT_MEM' mode, also shares memory space with FIFO mode. However, 'PAT_MEM' requires memory to be pre-reserved and waveform data to be pre-loaded. The entire 8K bytes of memory can be divided into partitions, and it is configurable, with FIFO mode always using the first partition [0, fifo_len], where 'fifo_len' is set via the 'MMAP_FIFO_REG' register. 'PAT_MEM' mode plays waveform using data preloaded in a memory bank defined by the registers 'PATX_MEM_START_ADDR_REG' and 'PATTERN_SPMI_PATX_LEN_REG' (they are not defined in the driver). Since PAT_MEM is mainly intended for hardware-triggered vibrations, such as a signal from a dedicated GPIO triggering a short vibration with a preloaded waveform, and although it also supports software triggers, I haven't found a suitable way to support it well into the driver under input FF framework yet. So, I am currently allocating the > entire 8K FIFO memory for FIFO mode only. We can adjust this later if we find a better way to incorporate 'PAT_MEM' mode into the driver. Sounds like a plan. For the other mode, would that GPIO trigger need any OS intervention? Could you speak a bit more about how that works? Konrad