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Wed, 05 Feb 2025 17:06:08 -0800 (PST) Content-Type: text/plain; charset=utf-8 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3826.300.87.4.3\)) Subject: Re: [PATCH 00/15] kasan: x86: arm64: risc-v: KASAN tag-based mode for x86 From: Jessica Clarke In-Reply-To: <72837fcd-97a8-c213-0098-c8f308c3415d@gentwo.org> Date: Thu, 6 Feb 2025 01:05:56 +0000 Cc: Maciej Wieczor-Retman , luto@kernel.org, xin@zytor.com, kirill.shutemov@linux.intel.com, palmer@dabbelt.com, tj@kernel.org, andreyknvl@gmail.com, brgerst@gmail.com, ardb@kernel.org, dave.hansen@linux.intel.com, jgross@suse.com, will@kernel.org, akpm@linux-foundation.org, arnd@arndb.de, corbet@lwn.net, dvyukov@google.com, richard.weiyang@gmail.com, ytcoode@gmail.com, tglx@linutronix.de, hpa@zytor.com, seanjc@google.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, justinstitt@google.com, jason.andryuk@amd.com, glider@google.com, ubizjak@gmail.com, jannh@google.com, bhe@redhat.com, vincenzo.frascino@arm.com, rafael.j.wysocki@intel.com, ndesaulniers@google.com, mingo@redhat.com, catalin.marinas@arm.com, junichi.nomura@nec.com, nathan@kernel.org, ryabinin.a.a@gmail.com, dennis@kernel.org, bp@alien8.de, kevinloughlin@google.com, morbo@google.com, dan.j.williams@intel.com, julian.stecklina@cyberus-technology.de, peterz@infradead.org, kees@kernel.org, kasan-dev@googlegroups.com, x86@kernel.org, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, llvm@lists.linux.dev, linux-doc@vger.kernel.org Content-Transfer-Encoding: quoted-printable Message-Id: <29A74A26-E922-4A4F-9B4A-8DB0336B99DF@jrtc27.com> References: <8bd9c793-aac6-a330-ea8f-3bde0230a20b@gentwo.org> <72837fcd-97a8-c213-0098-c8f308c3415d@gentwo.org> To: "Christoph Lameter (Ampere)" X-Mailer: Apple Mail (2.3826.300.87.4.3) On 5 Feb 2025, at 18:51, Christoph Lameter (Ampere) = wrote: >=20 > On Tue, 4 Feb 2025, Jessica Clarke wrote: >=20 >> It=E2=80=99s not =E2=80=9Cno performance penalty=E2=80=9D, there is a = cost to tracking the MTE >> tags for checking. In asynchronous (or asymmetric) mode that=E2=80=99s = not too >=20 >=20 > On Ampere Processor hardware there is no penalty since the logic is = build > into the usual read/write paths. This is by design. There may be on = other > platforms that cannot do this. You helpfully cut out all the explanation of where the performance penalty comes from. But if it=E2=80=99s as you say I can only assume = your design chooses to stall all stores until they have actually written, in which case you have a performance cost compared with hardware that omitted MTE or optimises for non-synchronous MTE. The literature on MTE agrees that it is not no penalty (but can be low penalty). I don=E2=80=99t= really want to have some big debate here about the ins and outs of MTE, it=E2=80=99s not the place for it, but I will stand up and point out = that claiming MTE to be =E2=80=9Cno performance penalty=E2=80=9D is = misrepresentative of the truth Jess