From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751490AbdBMXj1 (ORCPT ); Mon, 13 Feb 2017 18:39:27 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:41540 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751250AbdBMXj0 (ORCPT ); Mon, 13 Feb 2017 18:39:26 -0500 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 22996607E4 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=shankerd@codeaurora.org Reply-To: shankerd@codeaurora.org Subject: Re: [RFC PATCH 23/33] irqchip/gic-v3-its: Add VPENDBASER/VPROPBASER accessors References: <1484648454-21216-1-git-send-email-marc.zyngier@arm.com> <1484648454-21216-24-git-send-email-marc.zyngier@arm.com> To: Marc Zyngier , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu Cc: Thomas Gleixner , Jason Cooper From: Shanker Donthineni Message-ID: <29ab17b1-40c3-205b-cb6a-ea6fdbc96ac9@codeaurora.org> Date: Mon, 13 Feb 2017 17:39:23 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: <1484648454-21216-24-git-send-email-marc.zyngier@arm.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Marc, On 01/17/2017 04:20 AM, Marc Zyngier wrote: > V{PEND,PROP}BASER being 64bit registers, they need some ad-hoc > accessors on 32bit, specially given that VPENDBASER contains > a Valid bit, making the access a bit convoluted. > > Signed-off-by: Marc Zyngier > --- > arch/arm/include/asm/arch_gicv3.h | 28 ++++++++++++++++++++++++++++ > arch/arm64/include/asm/arch_gicv3.h | 5 +++++ > 2 files changed, 33 insertions(+) > > diff --git a/arch/arm/include/asm/arch_gicv3.h > b/arch/arm/include/asm/arch_gicv3.h > index 2747590..3f18832 100644 > --- a/arch/arm/include/asm/arch_gicv3.h > +++ b/arch/arm/include/asm/arch_gicv3.h > @@ -291,5 +291,33 @@ static inline u64 __gic_readq_nonatomic(const > volatile void __iomem *addr) > */ > #define gits_write_cwriter(v, c) __gic_writeq_nonatomic(v, c) > > +/* > + * GITS_VPROPBASER - hi and lo bits may be accessed independently. > + */ > +#define gits_write_vpropbaser(v, c) __gic_writeq_nonatomic(v, c) > + > +/* > + * GITS_VPENDBASER - the Valid bit must be cleared before changing > + * anything else. > + */ > +static inline void gits_write_vpendbaser(u64 val, void * __iomem addr) > +{ > + u32 tmp; > + > + tmp = readl_relaxed(addr + 4); > + if (tmp & GICR_PENDBASER_Valid) { > + tmp &= ~GICR_PENDBASER_Valid; > + writel_relaxed(tmp, addr + 4); > + } > + > + /* > + * Use the fact that __gic_writeq_nonatomic writes the second > + * half of the 64bit quantity after the first. > + */ > + __gic_writeq_nonatomic(val, addr); I'm not sure whether software has to check a register write pending bit GICR_CTLR.RWP or not. GICv3 spec says, the effect of a write to GICR_VPENDBASER register is not guaranteed to be visible throughout the affinity hierarchy,as indicated by GICR_CTLR.RWP == 0. -- Shanker Donthineni Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.