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Mon, 9 Jun 2025 11:45:21 -0700 From: Nicolin Chen To: , , , , CC: , , , , , Subject: [PATCH RFC v1 2/2] pci: Suspend ATS before doing FLR Date: Mon, 9 Jun 2025 11:45:14 -0700 Message-ID: <29cc1268dfdae2a836dbdeaa4eea3bedae564497.1749494161.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4F:EE_|DM6PR12MB4385:EE_ X-MS-Office365-Filtering-Correlation-Id: edb7308f-ded0-47ea-8aff-08dda785d3e8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?BMcuLIU23VKoB29OUdYuwZiFzjVwikhbI8aNZHfyM9y6Lf6SDO2JrHaRauKX?= =?us-ascii?Q?o5dZKm162G64dzvlaqKFSoAHVqxIjgD7t+pDPbXufm99ZMRiRXUme+MF1FZy?= =?us-ascii?Q?EPUAT12UhCitz9zAXq+P2LEA+ysuzXdbCBjQUgC66kLfaYMO9B3bb9QekvI9?= =?us-ascii?Q?EAVI5/sxUlrBwaIcMMO4DG+5shxmsQU9pbVD/TGP+hGe7VMz+U+GWprVPsDM?= =?us-ascii?Q?NaX5VhfgeSnkJeFq6ZxIuCjq76VLnqQbAXYIiSnqGiz2TuSk2fHCWRgJ2XLY?= =?us-ascii?Q?+a5n3QTwbMCiR/sgFjVyekSNBUfZoK3B9alvIigDFwb9j/RLpDxTEnTm7MDb?= =?us-ascii?Q?GQLH6mp1CKXCXoiKHqQbio6wvBEru2Z/ARQ8wNVWmph3IilwUvfoiREjKorw?= =?us-ascii?Q?OOdqtQCdtQIwgRdWNsVWLyVBr9AIkFxBodiNo5WzYCvJY7QFuyXhC4jvY4E7?= =?us-ascii?Q?UVFB979RSanlWCtoFACFr4LsawhKkwm/DllfcGyST6rqt5dD6rkdb+F7s9YX?= =?us-ascii?Q?hLLZi3e2uqGjtQtooCozFDq6TPWKjWUPF602O7WQpELRMGLidvz2GWu8g+OX?= =?us-ascii?Q?rEHmZOrZWSQlTgxzrzPaH45eNmJfOF1KFe+PyU93tOO3r+NEnui9LMDXB+10?= =?us-ascii?Q?RlKsejZjC2NKzyomOFHgIkrvmOu9ysgdN7VlaQmelU3R/Gl3n9gL+f+ZJsiS?= =?us-ascii?Q?L2EijvlYXl6YpyJIZVJIgSBpCm0ouf7GeplRnu5hpEz+/VOXso/T3k/5B963?= =?us-ascii?Q?20l/2tR0KRmpScUr/mPseq2qy7qc/YvKm0S0HjCwkXtQzfNvGgOhuAwdv7uX?= =?us-ascii?Q?WzWP8iEyeIyLdmbGRiy6dPHiKEdRGbLX5idDR2T5JLF9uUUWCDepwLW1t7sc?= =?us-ascii?Q?3lvvzoO+uRzDyR+d2xQOKTqYL74hIjqSJzK+SYm2nz3/ljvX/LtwiFE0UAIM?= =?us-ascii?Q?utf6rpv0/HEkdDWRqc0L/VqtaGXcThC35F5CV/RZOO9T4Rc8wSq7X3QwT02n?= =?us-ascii?Q?nR8IJtmI13DdLUSLH1dCJw1LnME2kOGfY/xWsFRAEG/H4YfJQx9RAkjDdlsZ?= =?us-ascii?Q?F0e/zYIyFPFoWPnyTMluJpXTd46v8Si2GlsTxcO3Ab+w8ljD+MuPlD/fAPE5?= =?us-ascii?Q?yBmX1dN/WLB/hTHroRs4af8t12Z0J9F4bIcwr+A3IAeQUKFLUTa+XI4ywTJw?= =?us-ascii?Q?IGsuEuxYovqtfCXzN4SwKmx3LKSMoScNThn6uCKXiOzhNUvq54vsjyF8o3CP?= =?us-ascii?Q?oTCJSkHv/Qz5P/hsr+NeXtB7b20Ds4fHQEkK34wpLGi0a5f+UL9We57cpCfz?= =?us-ascii?Q?ob74ML/JHEIP9iSd0wTuTGGunQqaDGVk11PeT7jWojzeFb88a3k9Qroz2qxx?= =?us-ascii?Q?C+DyzulASp3x9ErlUJ74o+fJrpdQdc8M4LJC/NhTzqTWDEUnh6dZ3UdCt1wF?= =?us-ascii?Q?69Q/z87BZOe0hHrQlv8zTTd4evDo4bqqgC+zTJ48eLX5LW4b99HfyoOL/3d7?= =?us-ascii?Q?zj7lUJTUlOneat6Qk/VePHnULa/4aaSjftvR?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jun 2025 18:45:38.2374 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: edb7308f-ded0-47ea-8aff-08dda785d3e8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4385 Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software should disable ATS before initiating a Function Level Reset. Call iommu_dev_reset_prepare() before FLR and iommu_dev_reset_done() after, in the two FLR Functions. This will dock the device at IOMMU_DOMAIN_BLOCKED during the FLR function, which should allow the IOMMU driver to pause DMA traffic and invode pci_disable_ats() and pci_enable_ats() respectively. Add a warning if ATS isn't disabled, in which case IOMMU driver should fix itself to disable ATS following the design in iommu_dev_reset_prepare(). Signed-off-by: Nicolin Chen --- drivers/pci/pci.c | 42 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 38 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index e9448d55113b..61535435bde1 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -4518,13 +4519,26 @@ EXPORT_SYMBOL(pci_wait_for_pending_transaction); */ int pcie_flr(struct pci_dev *dev) { + int ret = 0; + if (!pci_wait_for_pending_transaction(dev)) pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n"); + /* + * Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software disables ATS + * before initiating a Function Level Reset. So notify the iommu driver + * that actually enabled ATS. Have to call it after waiting for pending + * DMA transaction. + */ + if (iommu_dev_reset_prepare(&dev->dev)) + pci_err(dev, "failed to stop IOMMU\n"); + if (dev->ats_enabled) + pci_err(dev, "failed to stop ATS\n"); + pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); if (dev->imm_ready) - return 0; + goto done; /* * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within @@ -4533,7 +4547,11 @@ int pcie_flr(struct pci_dev *dev) */ msleep(100); - return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); + ret = pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); + +done: + iommu_dev_reset_done(&dev->dev); + return ret; } EXPORT_SYMBOL_GPL(pcie_flr); @@ -4561,6 +4579,7 @@ EXPORT_SYMBOL_GPL(pcie_reset_flr); static int pci_af_flr(struct pci_dev *dev, bool probe) { + int ret = 0; int pos; u8 cap; @@ -4587,10 +4606,21 @@ static int pci_af_flr(struct pci_dev *dev, bool probe) PCI_AF_STATUS_TP << 8)) pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n"); + /* + * Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software disables ATS + * before initiating a Function Level Reset. So notify the iommu driver + * that actually enabled ATS. Have to call it after waiting for pending + * DMA transaction. + */ + if (iommu_dev_reset_prepare(&dev->dev)) + pci_err(dev, "failed to stop IOMMU\n"); + if (dev->ats_enabled) + pci_err(dev, "failed to stop ATS\n"); + pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); if (dev->imm_ready) - return 0; + goto done; /* * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006, @@ -4600,7 +4630,11 @@ static int pci_af_flr(struct pci_dev *dev, bool probe) */ msleep(100); - return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); + ret = pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); + +done: + iommu_dev_reset_done(&dev->dev); + return ret; } /** -- 2.43.0