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Date: Tue, 6 Oct 2026 04:21:53 -0600 (MDT)
From: Paul Walmsley <pjw@kernel.org>
To: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com>
cc: Paul Walmsley <pjw@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, 
    Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alex@ghiti.fr>, 
    Himanshu Chauhan <himanshu.chauhan@oss.qualcomm.com>, 
    Conor Dooley <conor@kernel.org>, Anup Patel <anup@brainfault.org>, 
    =?ISO-8859-15?Q?Cl=E9ment_L=E9ger?= <cleger@rivosinc.com>, 
    Yunhui Cui <cuiyunhui@bytedance.com>, Atish Patra <atish.patra@linux.dev>, 
    Peter Zijlstra <peterz@infradead.org>, Ingo Molnar <mingo@redhat.com>, 
    Arnaldo Carvalho de Melo <acme@kernel.org>, 
    Namhyung Kim <namhyung@kernel.org>, Mark Rutland <mark.rutland@arm.com>, 
    Alexander Shishkin <alexander.shishkin@linux.intel.com>, 
    Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>, 
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    James Clark <james.clark@linaro.org>, Will Deacon <will@kernel.org>, 
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    Randy Dunlap <rdunlap@infradead.org>, 
    Shuah Khan <skhan@linuxfoundation.org>, Shuah Khan <shuah@kernel.org>, 
    Yuanzhu <yuanzhu@bytedance.com>, Yicong Yang <yang.yicong@picoheart.com>, 
    Susheng Yang <yang.susheng@zte.com.cn>, linux-riscv@lists.infradead.org, 
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    linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, 
    linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v10 0/9] riscv: add SBI Supervisor Software Events
 support
In-Reply-To: <20260911121456.33223-1-zhangzhanpeng.jasper@bytedance.com>
Message-ID: <29e631f0-c135-bea4-0a3b-81dd715cef54@kernel.org>
References: <20260911121456.33223-1-zhangzhanpeng.jasper@bytedance.com>
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Hi Zhanpeng Zhang,

On Fri, 11 Sep 2026, Zhanpeng Zhang wrote:

> RISC-V does not architecturally define a supervisor-mode non-maskable
> interrupt (NMI). An interrupt that arrives while Linux has cleared SIE stays
> pending and is not observed until interrupts are enabled again. That is
> correct for ordinary interrupt handling, but some kernel work needs an
> NMI-like notification that can run even inside an interrupt-disabled region:
> sampling a PMU overflow at the instruction that caused it, or taking a
> high-priority RAS report promptly, cannot wait for the next unmask boundary.
> 
> The SBI Supervisor Software Events (SSE) extension [1] fills this gap. It lets
> Linux register handlers for events that the SBI implementation can deliver
> ahead of ordinary traps and interrupts, giving RISC-V the NMI-like supervisor
> notification mechanism it otherwise lacks.

Thanks for taking this series forward.  Could you please rebase this 
series against the current riscv/for-next branch and repost?  I tried 
pulling the series in, but it needs quite a few updates since we've 
queued up quite a few patches that touch SBI.

thanks,


- Paul