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From: Alessio Belle <Alessio.Belle@imgtec.com>
To: "m.wilczynski@samsung.com" <m.wilczynski@samsung.com>
Cc: "lkp@intel.com" <lkp@intel.com>,
	Luigi Santivetti <Luigi.Santivetti@imgtec.com>,
	"tzimmermann@suse.de" <tzimmermann@suse.de>,
	"simona@ffwll.ch" <simona@ffwll.ch>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Frank Binns <Frank.Binns@imgtec.com>,
	"maarten.lankhorst@linux.intel.com"
	<maarten.lankhorst@linux.intel.com>,
	"mripard@kernel.org" <mripard@kernel.org>,
	"airlied@gmail.com" <airlied@gmail.com>
Subject: Re: [PATCH v3] drm/imagination: Align rogue_fwif_hwrtdata to 64 bytes
Date: Wed, 28 Oct 2026 14:43:32 +0000	[thread overview]
Message-ID: <29ed7e87285e39dfcb87c07d3c8a17361277f878.camel@imgtec.com> (raw)
In-Reply-To: <20260810-fix_imagination-v3-1-e512359722fc@samsung.com>

Hi Michal,

On Mon, 2026-08-10 at 12:20 +0200, Michal Wilczynski wrote:
> The build fails on RISC-V using GCC because `SIZE_CHECK(struct
> rogue_fwif_hwrtdata, 384)` expects 384 bytes, but the compiler generates
> a 336-byte structure.
> 
> This is due to an alignment conflict: the inner member `cleanup_state`
> requires 64-byte alignment, but the outer struct is explicitly marked
> `__aligned(8)`.
> 
> While GCC on ARM64 implicitly pads the size to a multiple of 64, GCC on
> RISC-V strictly respects the 8-byte outer alignment, resulting in a size
> mismatch.
> 
> Fix this by aligning the entire structure to 64 bytes, which resolves
> the contradiction and forces the correct 384 byte size on all
> architectures.
> 
> Fixes: a26f067feac1 ("drm/imagination: Add FWIF headers")
> Reported-by: kernel test robot <lkp@intel.com>
> Closes: https://lore.kernel.org/oe-kbuild-all/202512131851.1WNXk3BC-lkp@intel.com/
> Reviewed-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
> ---
> Changes in v3:
> - Cleaned up the changelog section by removing the accidental b4
>   "EDITME" template from v2.
> - No changes to the code or commit message.
> - Rebased patch on latest master.
> 
> Changes in v2:
> - Expanded the commit message to properly explain the root cause of the
>   GCC alignment conflict on RISC-V vs ARM64, based on v1 feedback.

Sorry to bother again on this. All versions have the same commit message as the
original. Do you still have the updated message that I think was meant to be
sent in v2? Or are you fine with me making these changes to the commit message
(+ rewrap) before applying this?

- "The build fails on RISC-V using GCC" -> "Sparse (W=1) builds fail"
- "While GCC on ARM64" -> "While a non-sparse build"
- "GCC on RISC-V strictly respects" -> "a sparse build strictly respects"
- "on all architectures" -> "on all builds"

Thanks,
Alessio

> - No changes to the code.
> ---
>  drivers/gpu/drm/imagination/pvr_rogue_fwif.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/imagination/pvr_rogue_fwif.h b/drivers/gpu/drm/imagination/pvr_rogue_fwif.h
> index 5d590c4c25663e431601dd26944465b62c31526b..2f8daa93c9e6832bbeec7460275c4b803792cb02 100644
> --- a/drivers/gpu/drm/imagination/pvr_rogue_fwif.h
> +++ b/drivers/gpu/drm/imagination/pvr_rogue_fwif.h
> @@ -2174,7 +2174,7 @@ struct rogue_fwif_hwrtdata {
>  	bool geom_caches_need_zeroing __aligned(4);
>  
>  	struct rogue_fwif_cleanup_ctl cleanup_state __aligned(64);
> -} __aligned(8);
> +} __aligned(64);
>  
>  /*
>   ******************************************************************************
> 
> ---
> base-commit: db2ddb87143519e20a95aa36c60b36107b736a58
> change-id: 20251222-fix_imagination-8ef0c94122c4
> 
> Best regards,


      reply	other threads:[~2026-10-28 14:44 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20260810102037eucas1p2f68492f185b4e411aafa83d5d15d0499@eucas1p2.samsung.com>
2026-08-10 10:20 ` Michal Wilczynski
2026-10-28 14:43   ` Alessio Belle [this message]

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