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b=LWtFz35q8p/GFAZhKSuWGBoEfXcqlsNfmuB9526hRqp8+GBwWUCD+YtaN2cWFkLcNbCyOqdfSvc8qOzbn3muvWlHPHP2AFbJc5o9SVXkH8YglpK5JlBw6UzzVJS3hRGnVxlib7F/4kFB3LQoaSSi7FZ2Xo44cBFGrqzzE5Xxp2U= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from PAVPR08MB9674.eurprd08.prod.outlook.com (2603:10a6:102:31d::14) by DB4PR08MB8173.eurprd08.prod.outlook.com (2603:10a6:10:383::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.23; Wed, 25 Feb 2026 13:48:54 +0000 Received: from PAVPR08MB9674.eurprd08.prod.outlook.com ([fe80::6f25:3681:7c97:ea2e]) by PAVPR08MB9674.eurprd08.prod.outlook.com ([fe80::6f25:3681:7c97:ea2e%5]) with mapi id 15.20.9632.017; Wed, 25 Feb 2026 13:48:54 +0000 Message-ID: <29efbd9b-f83c-408f-b43a-20ccc768814c@arm.com> Date: Wed, 25 Feb 2026 13:48:52 +0000 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 8/8] coresight: cti: Refactor cti_reg32_{show|store}() To: Leo Yan Cc: Suzuki Poulose , James Clark , Alexander Shishkin , Greg Kroah-Hartman , Mathieu Poirier , Yingchao Deng , Jie Gan , "coresight@lists.linaro.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , nd@arm.com References: <20260209-arm_coresight_cti_refactor_v1-v1-0-db71ab4d200b@arm.com> <20260209-arm_coresight_cti_refactor_v1-v1-8-db71ab4d200b@arm.com> <20260220173549.GI136967@e132581.arm.com> Content-Language: en-US From: Mike Leach In-Reply-To: <20260220173549.GI136967@e132581.arm.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: M9PIqgzADo+S7iZ0iFs2PYI4isa7tV6HCrzk27MZD6amVQq7ID11PrqxRQ7r95id1TnhS25ozlErOKuAHyC29Nka0s10DfyA8qzUQfI3DNmoN1L1yP4EH5DlaUJLsiIMwxrwf/PWmiIfC34mMmL50HYdapu6bd4hdr2spLUQTertl83z+Sefg0AEG26QsipQFHktrsT0tJJowS70pS54Dn2F0k404XIQKG37RSKF7JNUmOGpSV/Tx7CjM9uAJnaySPZtm6gRpeyRv/BhdeOPcKMrxhKCLfDDtO3isnT4adTo0s4+Xrt8dy4LSKYi1Eva6JrXar8x/jWfKmMe4msnEvke5cB7O3w/mXXSNFgBUN4ekC1XrflwlHqK09n0U8FROJIfj9olcOUG0QPWIox7s7QgDHoXHoCv22OQPFkv69OF7TITPhnFXPCvLX+cEGn9 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Feb 2026 13:49:56.3999 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6a9451eb-ee04-4a58-06b5-08de7474c2b7 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509F1.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR08MB8356 Hi Leo, On 2/20/26 17:35, Leo Yan wrote: > Hi Mike, > > On Fri, Feb 20, 2026 at 02:44:03PM +0000, Mike Leach wrote: > > [...] > >>> @@ -252,14 +252,14 @@ static ssize_t cti_reg32_show(struct device *dev, >>> char *buf, >>> struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); >>> struct cti_config *config = &drvdata->config; >>> >>> + if (reg_offset < 0) >>> + return -EINVAL; >>> + >>> scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) { >>> - if ((reg_offset >= 0) && cti_is_active(config)) { >>> + if (cti_is_active(config)) >>> val = cti_read_single_reg(drvdata, reg_offset); >>> - if (pcached_val) >>> - *pcached_val = val; >> >> I think we still need this. If a register with an none-zero default >> value / status that can change over time is read when active, then >> read when inactive, but never written, then the inactive value will >> not reflect the last read value. > > Let us consider below operations using your suggested approach: > > echo 0xab > /sys/bus/coresight/devices/cti_cpu0/regs/gate > cat /sys/bus/coresight/devices/cti_cpu0/regs/gate > > echo 1 > /sys/bus/coresight/devices/cti_cpu0/enable > cat /sys/bus/coresight/devices/cti_cpu0/regs/gate > > echo 0 > /sys/bus/coresight/devices/cti_cpu0/enable > cat /sys/bus/coresight/devices/cti_cpu0/regs/gate > > If a user reads the "gate" knob three times in the above flow, it ends > up having three different semantics. > > - The first "cat ../gate" outputs the user specified value (0xab). > - The second "cat" outputs the real-time register value after the > module has been enabled. which for a non volatile register will be 0xab as enable writes all the regs from the config to the device - or will have been written through the cache to the device by the echo command if the device was powered and available . > - The third "cat" outputs the last read value before disabling. > Still 0xab unless this is a register that can change do to operation in which case it will be whatever the last noted value is. All of the above is entirely expected and required. We should always show the user the latest value of the register. If the CTI is powered and available then this will be that directly read from the register. The ETM is not different in this respect, except that the ETM reads all registers back on disable - and registers are architecturally forbidden to be written while the device is enabled - unlike the CTI where registers can be written after the device is enabled, and for some registers it makes sense only to write them when enabled. With the CTI we do not readback all the regs at disable. They are demand read for sysfs, which is more efficient. > This could be confusing for users (even for ourseleves), as it needs to > understand the meaning of the value under specific conditions and based > on prior operations. > That is pretty much the definition of reading a hardware register on any device. You need to know if it can change during operation or not, if it is volatile under the conditions you are reading it. > To simplify the semantics in this patch, the "cat" returns the realtime > register value when the module is enabled; otherwise, it returns the > user configured value. Since "*pcached_val" always stores the user > configuration, it remains consistent configurations across multiple > enable/disable cycles. The semantics of the cache are to use it if the registers are unavailable if not powered. > >> Relatively minor issue but does represent a potential change in >> functionality for the driver - even if I cannot see specific issues >> for current ARM CTIs. This is a R/W cache so should be updated on >> both R and W. > > "R/W cache" mixes the cached user configured value with the hardware > register dump and may become inconsistent across multiple > enable/disable cycles. > > It seems to me that this is a bit overdesigned and complex. thoughts? > RW caching has been around for a long time - not sure 2 lines of code could be described as complex! Regards Mike > Thanks a lot for review! > > Leo