From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46A55C77B70 for ; Fri, 14 Apr 2023 08:20:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230106AbjDNIUM (ORCPT ); Fri, 14 Apr 2023 04:20:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230025AbjDNIUH (ORCPT ); Fri, 14 Apr 2023 04:20:07 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 72AFF30EA for ; Fri, 14 Apr 2023 01:20:06 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AD03C2F4; Fri, 14 Apr 2023 01:20:50 -0700 (PDT) Received: from [10.57.19.162] (unknown [10.57.19.162]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F19343F6C4; Fri, 14 Apr 2023 01:20:01 -0700 (PDT) Message-ID: <2a05dac0-c57e-a3cd-ec4d-55cf32e6dce9@arm.com> Date: Fri, 14 Apr 2023 10:19:56 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH v3 2/4] cacheinfo: Check cache properties are present in DT Content-Language: en-US To: Florian Fainelli , linux-kernel@vger.kernel.org Cc: Radu Rendec , Alexandre Ghiti , Conor Dooley , Will Deacon , Sudeep Holla , Greg Kroah-Hartman , "Rafael J. Wysocki" , Palmer Dabbelt , Gavin Shan References: <20230413091436.230134-1-pierre.gondois@arm.com> <20230413091436.230134-3-pierre.gondois@arm.com> <4da53918-839b-4d28-0634-66fd7f38c8bd@gmail.com> From: Pierre Gondois In-Reply-To: <4da53918-839b-4d28-0634-66fd7f38c8bd@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello Florian, On 4/13/23 20:16, Florian Fainelli wrote: > On 4/13/23 02:14, Pierre Gondois wrote: >> If a Device Tree (DT) is used, the presence of cache properties is >> assumed. Not finding any is not considered. For arm64 platforms, >> cache information can be fetched from the clidr_el1 register. >> Checking whether cache information is available in the DT >> allows to switch to using clidr_el1. >> >> init_of_cache_level() >> \-of_count_cache_leaves() >> will assume there a 2 cache leaves (L1 data/instruction caches), which >> can be different from clidr_el1 information. >> >> cache_setup_of_node() tries to read cache properties in the DT. >> If there are none, this is considered a success. Knowing no >> information was available would allow to switch to using clidr_el1. >> >> Fixes: de0df442ee49 ("cacheinfo: Check 'cache-unified' property to count cache leaves") >> Reported-by: Alexandre Ghiti >> Link: https://lore.kernel.org/all/20230404-hatred-swimmer-6fecdf33b57a@spud/ >> Signed-off-by: Pierre Gondois > > Humm, it would appear that the cache levels and topology is still > provided, despite the lack of cache properties in the Device Tree which > is intended by this patch set however we lost the size/ways/sets > information, could we not complement the missing properties here? > > If this is out of the scope of what you are doing: > > Tested-by: Florian Fainelli I submitted a v4 at: https://lore.kernel.org/all/20230414081453.244787-1-pierre.gondois@arm.com/ I haven't included your Tested-by as there were some small changes. If you consider these changes are small enough to include your tag, please let know, Regards, Pierre