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Fri, 26 Jun 2026 07:54:39 -0700 (PDT) X-Received: by 2002:a17:902:c40a:b0:2c0:a555:80e6 with SMTP id d9443c01a7336-2c7fc654109mr75502655ad.6.1782485679097; Fri, 26 Jun 2026 07:54:39 -0700 (PDT) Received: from [192.168.29.96] ([49.37.170.88]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c7f5ac899esm41390565ad.7.2026.06.26.07.54.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 26 Jun 2026 07:54:38 -0700 (PDT) Message-ID: <2a52ecb1-be8a-4522-aa23-f3277f0555fa@oss.qualcomm.com> Date: Fri, 26 Jun 2026 20:24:31 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: harsha.v@oss.qualcomm.com Subject: Re: [PATCH v2 00/11] iommu/arm-smmu-v3: Add PRI support To: Nicolin Chen , will@kernel.org, robin.murphy@arm.com, jgg@nvidia.com Cc: joro@8bytes.org, bhelgaas@google.com, praan@google.com, kevin.tian@intel.com, kees@kernel.org, smostafa@google.com, baolu.lu@linux.intel.com, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, skaestle@nvidia.com, mmarrid@nvidia.com, skolothumtho@nvidia.com, bbiber@nvidia.com References: Content-Language: en-GB In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI2MDEyMyBTYWx0ZWRfXy14EmB5yxtAW 0IMmu2qQsPMZvgwud+qvC/TIrKWG0F8krlfpcokJkUPABcafaILmkwSvifZUvn5eGKLay5O7vuS BgxMyN/enQV2i1cdobquxDoLrXmCiJ8HFcEcI1pSewlOubG+u0VgX02pDBBL1bP6SlBEhmDU4Rl stw8wNvg9y8wggK5xQBVhSWOk/edIlSbTFBcJo4TOp+VqwaKc91eMfv9FIlircyj9qR4lYZAqnI stjhOMVCekv+Cg+lkRKJI+l+PFWE6QeEnpHIi6wC5qhb6A9BVoUU9emnRA8wAEw33hVLqwq9TTx GKXS5yXv/aLTEpECX1LFyw/kRDShPD8iKaDqRF0k9GMs08h7PUvehF2+pH6tgo/Us2QuB8ELPoV LsT1RVPG16e7gwEzS4gSjcTkIgtJHQILy31SX45fAGG2RJN4FFIXXtLL/ZxzrzU1NSu58+hsa2v zzWvUW/IjeBEIDxdctw== X-Authority-Analysis: v=2.4 cv=KNlqylFo c=1 sm=1 tr=0 ts=6a3e92b0 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=asHclmMlXTalQ/2ShlWtEQ==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=NEAV23lmAAAA:8 a=VwQbUJbxAAAA:8 a=Ikd4Dj_1AAAA:8 a=XZ8z-I0mWLgmP2cXQ10A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI2MDEyMyBTYWx0ZWRfX/vLVaNXjpeXf NhLg4h0wERy7tJs2KIWcg3912eYXpOlomyYSiWAgBIs1M30aG2t60ybHZvaaGycFcIggoHaGZv7 MRU70vXyFmZNUJKnULVPcvVQmS95Kqw= X-Proofpoint-ORIG-GUID: 8cAncDUBow3YOGtME7nNYLf_OX8GRz_8 X-Proofpoint-GUID: 8cAncDUBow3YOGtME7nNYLf_OX8GRz_8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-26_03,2026-06-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 malwarescore=0 spamscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606260123 Hi Nicolin Chen, On 5/28/2026 1:29 PM, Nicolin Chen wrote: > The SMMUv3 driver doesn't handle events on the PRI queue or respond to IOPF > faults. This series adds the missing pieces, using the IOPF infrastructure, > to convert PRI page requests into iopf_faults and issue CMDQ_OP_PRI_RESP. > > The iopf_queue_flush_dev() contract requires the driver to first drain the > hardware PRI queue and synchronize using a threaded IRQ handler before the > IOPF software flush. This drove the additional commits compared to v1: > - arm_smmu_drain_queue_for_iopf() drains the hardware queue to the PROD > snapshot > - arm_smmu_attach_release() moves the teardown outside the global lock > - synchronize_irq() closes the gap before the final flush > > This is on Github: > https://github.com/nicolinc/iommufd/commits/smmuv3_pri-v2 > > FWIW, engineers on the NVIDIA side have managed to verify the PRI feature. > > Changelog > v2: > * Allocate evtq.iopf for ARM_SMMU_FEAT_PRI > * Pick up Jean's PRI stubs and PRI export patches > * Enable PRI for PCI devices in arm_smmu_probe_device() > * Add arm_smmu_drain_queue_for_iopf() for EVTQ and PRIQ > * Add arm_smmu_attach_release() to rework the IOPF drain > * Add IOMMU_FAULT_PAGE_REQUEST_STALLS_TRANS for STALL mode > * Gate pci_enable_pri() on FEAT_PRI plus a non-NULL evtq.iopf > * Deny unrecognised-StreamID PRG_LAST in arm_smmu_handle_ppr() > * Disable PRI when no IRQ handler is registered (unique or combined IRQ) > v1: > https://lore.kernel.org/all/cover.1772568590.git.nicolinc@nvidia.com/ > > Jean-Philippe Brucker (2): > PCI/ATS: Add PRI stubs > PCI/ATS: Export pci_enable_pri() and pci_reset_pri() > > Malak Marrid (1): > iommu/arm-smmu-v3: Submit CMDQ_OP_PRI_RESP for IOPF event > > Nicolin Chen (8): > iommu/arm-smmu-v3: Add arm_smmu_attach_release() > iommu/arm-smmu-v3: Factor out __queue_empty() and __queue_consumed() > iommu/arm-smmu-v3: Add arm_smmu_drain_queue_for_iopf() helper > iommu/arm-smmu-v3: Drain in-flight fault handlers > iommu/arm-smmu-v3: Support PRI Page Request in arm_smmu_handle_ppr() > iommu/arm-smmu-v3: Disable PRI when no IRQ handler is registered > iommu/arm-smmu-v3: Allocate IOPF queue for ARM_SMMU_FEAT_PRI > iommu/arm-smmu-v3: Enable PRI for PCI device in > arm_smmu_probe_device() > > drivers/iommu/arm/Kconfig | 1 + > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 + > include/linux/iommu.h | 1 + > include/linux/pci-ats.h | 5 + > .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 1 + > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 244 +++++++++++++++--- > drivers/pci/ats.c | 2 + > 7 files changed, 221 insertions(+), 36 deletions(-) > > > base-commit: 74fa4c177ad09800b007cba043370c887bb1b4e3 One thing I noticed while reviewing: when arm_smmu_priq_thread() detects PRIQ overflow, partial faults (non-LAST pages stored via report_partial_fault()) whose LAST page was lost in the overflow remain permanently in iopf_param->partial. This is a monotonic memory leak — it grows with each overflow event. Intel VT-d handles this in prq_event_thread() (drivers/iommu/intel/prq.c): if (head == tail) { iopf_queue_discard_partial(iommu->iopf_queue); writel(DMA_PRS_PRO, iommu->reg + DMAR_PRS_REG); } iopf_queue_discard_partial() was written for exactly this scenario. Could we add the same here arm_smmu_priq_thread() (drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c) ? if (queue_sync_prod_in(q) == -EOVERFLOW) { dev_err(smmu->dev, "PRIQ overflow detected -- requests lost\n"); + iopf_queue_discard_partial(smmu->evtq.iopf); } At this point all surviving entries have already been consumed by the loop above, so discarding unconditionally is safe — implicitly matching Intel's "head == tail" guard. Best Regards, Harsha Vardhan V