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Mon, 06 Jul 2026 14:56:22 -0700 (PDT) X-Received: by 2002:a17:90b:3a48:b0:37f:ee3a:12a with SMTP id 98e67ed59e1d1-387d6b978a7mr102043a91.2.1783374981910; Mon, 06 Jul 2026 14:56:21 -0700 (PDT) Received: from [192.168.1.9] ([106.222.230.254]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-311748394acsm762251eec.8.2026.07.06.14.56.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Jul 2026 14:56:21 -0700 (PDT) Message-ID: <2a556ca0-d276-4c56-a44e-9d8b92a3af6b@oss.qualcomm.com> Date: Tue, 7 Jul 2026 03:26:11 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC 10/13] drm/msm: initialize LPAC ring To: Anna Maniscalco , Konrad Dybcio , Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org References: <20260705-descriptive-name-lpac-upstream-v1-0-01d50c3e0c99@gmail.com> <20260705-descriptive-name-lpac-upstream-v1-10-01d50c3e0c99@gmail.com> <93b78299-866f-4a3c-9423-a990d9a7d4cd@oss.qualcomm.com> <64a919ab-8b36-45fe-8da8-5eaaf4d55359@gmail.com> From: Akhil P Oommen Content-Language: en-US In-Reply-To: <64a919ab-8b36-45fe-8da8-5eaaf4d55359@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: 4OjB8oNbu_BWxGzog82weEKyndHCzD44 X-Proofpoint-ORIG-GUID: 4OjB8oNbu_BWxGzog82weEKyndHCzD44 X-Authority-Analysis: v=2.4 cv=CPYamxrD c=1 sm=1 tr=0 ts=6a4c2487 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=fsdq8dFr2Uux402FS9br8A==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=pGLkceISAAAA:8 a=mx_oZ8J27MAni7-wUjsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA2MDIyMSBTYWx0ZWRfX3bMofQVFlfCl lEegAVPXAAbBuZygUABnTEPD0y4RykNvaZj8J5gh/RBfNP4grSGFA7QO7olfoFMJwIM+td205c0 7CpomIdDEbw0wEcI69nO3MZq9PmJMTMRGimCJp4Q1Y1ITSw1PT/n/eCztg8L5eDwbL8xzhgj0aw uhUa7oJ447kP4OdcTY8clgogodwWDdrwK28SPxfm5Mw2IlwwP/VpO3ceiMNjLcMq/PwUEMW7ac1 HruWCdgU2bNEe5rwv8e/H/u0Qc34E/BschmMwcQ1JemYthGzdT5VvTAqU/81X6US4FlCqtcRPyq qTJ688EofbVJHkQHkkPW/hNb0lCd5S9so5ACJX8riYHdMKYQ0JGm4BKlYh1IDgyWH8sxXV7WyeG 8z3GehCkcw2DgJ2viEEmkVztCFMy34qjNmXv9GCf7yB1qeIUx2HkKxIO7a6//axHTc4bo2xA+Lp Pj3aSOy4u+8UvuvvkHg== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA2MDIyMSBTYWx0ZWRfX2JQuKQLwsQgq anJeD36rV7y8vOlGROxkYEwWt/DK94NcvPBRWADnu5WbUS0P/xJaaSWH+Hk7KeuP8SAIJ4SRLiK 7wd4OW5jfjpMxgcXqzREM3EwssO1juk= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-06_03,2026-07-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607060221 On 7/6/2026 4:37 PM, Anna Maniscalco wrote: > On 7/6/26 10:44 AM, Konrad Dybcio wrote: >> On 7/5/26 9:13 PM, Anna Maniscalco wrote: >>> Program all the register needed to start up LPAC and send initialization >>> sequence. >>> >>> Additionally, now that the LPAC ring is live, make the code aware of it. >>> >>> Signed-off-by: Anna Maniscalco >>> --- >> I believe some/all of these writes need to be guarded by if (has_lpac), >> as many GPUs lack these registers and there may be side effects on >> others > > That's correct yeah. I'm not sure what has_lpac should be though. > > Something we add to catalog? Or checking if it is a gen that has LPAC? We can introduce a new QUIRK (ADRENO_QUIRK_LPAC?). > >> >> >> [...] >> >>>           a6xx_gpu->shadow = msm_gem_kernel_new(gpu->dev, >>> -                              sizeof(u32) * gpu->nr_rings, >>> +                              sizeof(u32) * (gpu->nr_rings + !!gpu- >>> >lpac_rb), >> Should we rename nr_rings to something like nr_XXX_rings >> where XXX is some uarch-generic (i.e. not SQE because we also >> support pre-a6xx) name for the main number cruncher? > Qualcom calls it GC so nr_gc_rings perhaps? How about nr_gfx_rings as those rings can handle graphics workload? -Akhil. >> >> Konrad > > > Best regards,