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Wed, 30 Oct 2024 18:03:49 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49UI3mGo017094 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Oct 2024 18:03:48 GMT Received: from [10.216.35.255] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 30 Oct 2024 11:03:42 -0700 Message-ID: <2aa768a4-b0e9-4b2f-8d74-736a88cf81cd@quicinc.com> Date: Wed, 30 Oct 2024 23:33:39 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 08/11] clk: qcom: gpucc-qcs615: Add QCS615 graphics clock controller driver To: Dmitry Baryshkov CC: Bjorn Andersson , Michael Turquette , Stephen Boyd , Abhishek Sahu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Ajit Pandey , Imran Shaik , "Jagadeesh Kona" , Stephen Boyd , , , , , References: <20241019-qcs615-mm-clockcontroller-v1-0-4cfb96d779ae@quicinc.com> <20241019-qcs615-mm-clockcontroller-v1-8-4cfb96d779ae@quicinc.com> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: KWrR1kyKUunE9PWKLs18ZnYkiaBmlu4v X-Proofpoint-GUID: KWrR1kyKUunE9PWKLs18ZnYkiaBmlu4v X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 bulkscore=0 adultscore=0 spamscore=0 phishscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 mlxscore=0 mlxlogscore=781 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410300142 On 10/19/2024 1:58 AM, Dmitry Baryshkov wrote: >> +static struct gdsc gx_gdsc = { >> + .gdscr = 0x100c, >> + .en_rest_wait_val = 0x2, >> + .en_few_wait_val = 0x2, >> + .clk_dis_wait_val = 0x2, >> + .pd = { >> + .name = "gx_gdsc", > .power_on = gdsc_gx_do_nothing_enable ? Or is it controlled directly on > this platform? > On QCS615 the GPU clocks are directly controlled by high level OS. >> + }, >> + .pwrsts = PWRSTS_OFF_ON, >> + .flags = POLL_CFG_GDSCR, >> +}; >> + -- Thanks & Regards, Taniya Das.