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([2600:8803:e7e4:500:1635:b560:bfdd:f758]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4537f6bc9d5sm8556424b6e.0.2025.12.09.16.02.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Dec 2025 16:02:05 -0800 (PST) Message-ID: <2aca99a6-9541-4cd4-933e-815ceaabe365@baylibre.com> Date: Tue, 9 Dec 2025 18:02:03 -0600 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 4/7] spi: axi-spi-engine: support SPI_MULTI_LANE_MODE_STRIPE To: Andy Shevchenko Cc: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?UTF-8?Q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko , Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org References: <20251201-spi-add-multi-bus-support-v3-0-34e05791de83@baylibre.com> <20251201-spi-add-multi-bus-support-v3-4-34e05791de83@baylibre.com> Content-Language: en-US From: David Lechner In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 12/2/25 8:53 AM, Andy Shevchenko wrote: > On Mon, Dec 01, 2025 at 08:20:42PM -0600, David Lechner wrote: >> Add support for SPI_MULTI_LANE_MODE_STRIPE to the AXI SPI engine driver. >> >> The v2.0.0 version of the AXI SPI Engine IP core supports multiple >> lanes. This can be used with SPI_MULTI_LANE_MODE_STRIPE to support >> reading from simultaneous sampling ADCs that have a separate SDO line >> for each analog channel. This allows reading all channels at the same >> time to increase throughput. > > ... > >> +static u8 spi_engine_all_lane_flags(struct spi_device *spi) >> +{ >> + u8 flags = 0; > >> + int i; > > Why signed? Because it is conventional. > >> + for (i = 0; i < spi->num_data_lanes; i++) >> + flags |= BIT(spi->data_lanes[i]); >> + >> + return flags; >> +} > > ... > >> static void spi_engine_gen_xfer(struct spi_engine_program *p, bool dry, >> - struct spi_transfer *xfer) >> + struct spi_transfer *xfer, u32 num_lanes) > > Side note: this bool parameter makes code harder to follow. And now we have > pointers and integers/booleans to be interleaved. Perhaps reconsider the order > of the parameters (and ideally get rid of boolean by making two distinct > functions?). There would be significant code duplication if we split this which would make it error prone. Perhaps a bit unusual parameter ordering according to data type, but they are grouped logically, so I think it is OK. `dry` affects what is written to `p` and `num_lanes` supplements `xfer`. > > ... > >> version = readl(spi_engine->base + ADI_AXI_REG_VERSION); >> - if (ADI_AXI_PCORE_VER_MAJOR(version) != 1) { >> + if (ADI_AXI_PCORE_VER_MAJOR(version) > 2) { > > But this includes v0 as well! I think it is OK. There was never a version 0 released, nor is one expected. > >> } >