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Fri, 31 Jul 2026 09:28:46 -0700 (PDT) X-Received: by 2002:ac8:7e81:0:b0:51c:845b:ac4 with SMTP id d75a77b69052e-52b567f85bamr10459421cf.3.1785515325767; Fri, 31 Jul 2026 09:28:45 -0700 (PDT) Received: from [192.168.120.193] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c1fd44542d2sm229079466b.35.2026.07.31.09.28.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 31 Jul 2026 09:28:44 -0700 (PDT) Message-ID: <2ace2703-79cb-4046-a2b3-8fdeb9b2c99e@oss.qualcomm.com> Date: Fri, 31 Jul 2026 18:28:42 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] dt-bindings: soc: qcom: qcom,pmic-glink: Add compatible string for SM8475 To: Esteban Urrutia , Krzysztof Kozlowski Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heikki Krogerus , Greg Kroah-Hartman , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, phone-devel@vger.kernel.org References: <20260731-sm8475-pmic-glink-v2-0-28c04928ef22@proton.me> <20260731-sm8475-pmic-glink-v2-1-28c04928ef22@proton.me> <20260731-savvy-piquant-chowchow-f516f2@quoll> <9718d7b8-7303-47a2-9d75-58bbde6385e9@proton.me> <6fc5165c-95b5-475a-a0a6-e1d7b9721222@proton.me> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <6fc5165c-95b5-475a-a0a6-e1d7b9721222@proton.me> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMxMDEyNSBTYWx0ZWRfX/YY/KArhX5R+ OqjHI7Ijine1KO1o7XUGW49osRDCUn/ibWlHW5sVtYzGdRB4XiHTVlz/8mMXXDV+C8SL8/hRNcz VeLOZvLBjWFQpVlIn0YVGrx9LTsfAng= X-Proofpoint-GUID: izXC6Fa2GH2h1t7ygHB0o8T5_ae8PRjH X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMxMDEyNSBTYWx0ZWRfX+f329gM0SCpq V7em9u8dvH+91jwPI/7t2bZoEii8T8YvP4sTXvblmWZzdjE9KPvSduwPt1p8+cYLqp5WfZx4r0f +05XzFFBBTBI3rZmCc9CG+Gr+RJ49fLxEGOGYUHbn0HQXMvydLDweZ6+pO/UEjJHf0tGMOERCKD ZvDYryZYHbfwJ9LU+gEp9XyblXMifIvK5XPENWSN34gtYBfLxSJHBNkM7GGH33uO1yvQ07+7RR6 os9yJ020GdRPm+jWeS1dnI2VMNBWkLL+gMMyiT+l3pRSxG5IaNOGCDAa/20kbYLAS9BWhtrUnF+ womPdu3dW7G8nFYA8hpIGBG7YAvvQSn/0MpV3F7LYwxd2aVFJeLMdnUuY+5oMT1Lk/KhKBzmNti nskFItCbYOldt8gqdLOIKWC7Y8aSjUowxkZUspljqXcU6SKnBf75p6C4SICxwa6ImZjlrRavXBB VVnfjT5hUwxqAvotb/Q== X-Proofpoint-ORIG-GUID: izXC6Fa2GH2h1t7ygHB0o8T5_ae8PRjH X-Authority-Analysis: v=2.4 cv=CYI4Irrl c=1 sm=1 tr=0 ts=6a6ccd3f cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=P4BrIvBfxGhJqZf7NZgA:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-31_05,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 bulkscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607310125 On 7/31/26 5:54 PM, Esteban Urrutia wrote: > On 7/31/26 11:30 AM, Konrad Dybcio wrote: >> On 7/31/26 4:44 PM, Esteban Urrutia wrote: >>> On 7/31/26 5:58 AM, Krzysztof Kozlowski wrote: >>>> On Fri, Jul 31, 2026 at 01:00:08AM -0400, Esteban Urrutia wrote: >>>>> Due to a different process design, SM8475 (4 nm) SoC takes things from both >>>>> SM8450 (4 LPX) and SM8550 (4 nm) SoCs. >>>> >>>> What things? This is just unspecific and not useful. And I doubt that it >>>> is even "different process design", because how one would know that? >>> >>> >>> The process design is specified on the corresponding datasheets for >>> these SoCs, which are flying somewhere around the internet. >>> Also [1]. >>> >>>>> Add a separate compatible string for this SoC to avoid possible confusions. >>>> >>>> No, explain the hardware compatibility. >>>> >>>> Add foo bar, which is not compatible with baz because it uses bam bam in >>>> different setup (difference in registers, e.g. XYZ and ABC), >>> >>> How does this commit message based on what was said in [1] sound to you? >> >> That made more sense because the electrical differences are what made >> the PHY init sequence changes necessary. Here, Krzysztof is trying to >> express that the pmic-glink interface found on SM8475 is likely no >> different than the one found on SM8450 (and SM8350 and so on) >> >> Then, since it's the same, it can reuse the same driver match data, >> so patch 2 is unnecessary, since the driver binds said match data >> on the fallback "qcom,pmic-glink" compatible > > > I don't understand. You're implying that the pmic-glink interface found > on SM8350 and SM8450 is not that different but they both have different > quirks on ucsi_glink.c. > No quirks would be applied on SM8475 if patch 2 is not in place either. Somehow I confabulated the generic compatible being present in the driver... I was trying to explain that And yes I didn't notice the 8350/8450 difference. But anyway, the resolution will be one of: // 8450 is fully compatible "qcom,sm8475-pmic-glink", "qcom,sm8450-pmic-glink", "qcom,pmic-glink" or // 8475 is special "qcom,sm8475-pmic-glink", "qcom,pmic-glink" depending on what you believe is more correct. I think the first one fits better. Konrad