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Thu, 15 Aug 2024 23:30:42 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47FNUfpX005445 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 23:30:41 GMT Received: from [10.46.19.239] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 15 Aug 2024 16:30:40 -0700 Message-ID: <2ad03012-8a10-49fc-9e80-3b91762b9cc3@quicinc.com> Date: Thu, 15 Aug 2024 16:30:31 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [net-next v4 1/5] net: stmmac: Add HDMA mapping for dw25gmac support To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Sagar Cheluvegowda References: <20240814221818.2612484-1-jitendra.vegiraju@broadcom.com> <20240814221818.2612484-2-jitendra.vegiraju@broadcom.com> Content-Language: en-US From: "Abhishek Chauhan (ABC)" In-Reply-To: <20240814221818.2612484-2-jitendra.vegiraju@broadcom.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: D26Z6C0OL0tCkQUExsEuaABgFByfXNjD X-Proofpoint-ORIG-GUID: D26Z6C0OL0tCkQUExsEuaABgFByfXNjD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-15_15,2024-08-15_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 malwarescore=0 spamscore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 clxscore=1011 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408150171 On 8/14/2024 3:18 PM, jitendra.vegiraju@broadcom.com wrote: > From: Jitendra Vegiraju > > Add hdma configuration support in include/linux/stmmac.h file. > The hdma configuration includes mapping of virtual DMAs to physical DMAs. > Define a new data structure stmmac_hdma_cfg to provide the mapping. > > Signed-off-by: Jitendra Vegiraju > --- > include/linux/stmmac.h | 50 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 50 insertions(+) > > diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h > index 338991c08f00..1775bd2b7c14 100644 > --- a/include/linux/stmmac.h > +++ b/include/linux/stmmac.h > @@ -89,6 +89,55 @@ struct stmmac_mdio_bus_data { > bool needs_reset; > }; > > +/* DW25GMAC Hyper-DMA Overview > + * Hyper-DMA allows support for large number of Virtual DMA(VDMA) > + * channels using a smaller set of physical DMA channels(PDMA). > + * This is supported by the mapping of VDMAs to Traffic Class (TC) > + * and PDMA to TC in each traffic direction as shown below. > + * > + * VDMAs Traffic Class PDMA > + * +--------+ +------+ +-----------+ > + * |VDMA0 |--------->| TC0 |-------->|PDMA0/TXQ0 | > + *TX +--------+ |----->+------+ +-----------+ > + *Host=> +--------+ | +------+ +-----------+ => MAC > + *SW |VDMA1 |---+ | TC1 | +--->|PDMA1/TXQ1 | > + * +--------+ +------+ | +-----------+ > + * +--------+ +------+----+ +-----------+ > + * |VDMA2 |--------->| TC2 |-------->|PDMA2/TXQ1 | > + * +--------+ +------+ +-----------+ > + * . . . > + * +--------+ +------+ +-----------+ > + * |VDMAn-1 |--------->| TCx-1|-------->|PDMAm/TXQm | > + * +--------+ +------+ +-----------+ > + * > + * +------+ +------+ +------+ > + * |PDMA0 |--------->| TC0 |-------->|VDMA0 | > + * +------+ |----->+------+ +------+ > + *MAC => +------+ | +------+ +------+ > + *RXQs |PDMA1 |---+ | TC1 | +--->|VDMA1 | => Host > + * +------+ +------+ | +------+ > + * . . . > + */ > + > +#define STMMAC_DW25GMAC_MAX_NUM_TX_VDMA 128 > +#define STMMAC_DW25GMAC_MAX_NUM_RX_VDMA 128 > + > +#define STMMAC_DW25GMAC_MAX_NUM_TX_PDMA 8 > +#define STMMAC_DW25GMAC_MAX_NUM_RX_PDMA 10 > + I have a query here. Why do we need to hardcode the number of TX PDMA and RX PDMA to 8 an 10. On some platforms the number of supported TXPDMA and RXPDMA are 11 and 11 respectively ? how do we overcome this problem, do we increase the value in such case? > +#define STMMAC_DW25GMAC_MAX_TC 8 > + > +/* Hyper-DMA mapping configuration > + * Traffic Class associated with each VDMA/PDMA mapping > + * is stored in corresponding array entry. > + */ > +struct stmmac_hdma_cfg { > + u8 tvdma_tc[STMMAC_DW25GMAC_MAX_NUM_TX_VDMA]; > + u8 rvdma_tc[STMMAC_DW25GMAC_MAX_NUM_RX_VDMA]; > + u8 tpdma_tc[STMMAC_DW25GMAC_MAX_NUM_TX_PDMA]; > + u8 rpdma_tc[STMMAC_DW25GMAC_MAX_NUM_RX_PDMA]; > +}; > + > struct stmmac_dma_cfg { > int pbl; > int txpbl; > @@ -101,6 +150,7 @@ struct stmmac_dma_cfg { > bool multi_msi_en; > bool dche; > bool atds; > + struct stmmac_hdma_cfg *hdma_cfg; > }; > > #define AXI_BLEN 7