From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754251AbdLGQuF (ORCPT ); Thu, 7 Dec 2017 11:50:05 -0500 Received: from mail-wr0-f194.google.com ([209.85.128.194]:41624 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753870AbdLGQuA (ORCPT ); Thu, 7 Dec 2017 11:50:00 -0500 X-Google-Smtp-Source: AGs4zMY8obANlm+olTvpKZJYYu1qEd/WpRDxSuyvnho84cJUb+NO7g2+Ctjd1sWE37O+2rAMFKTJNQ== Subject: Re: [PATCH v8 4/6] clocksource: stm32: only use 32 bits timers To: Benjamin Gaignard Cc: Rob Herring , Mark Rutland , Russell King - ARM Linux , Maxime Coquelin , Alexandre Torgue , Thomas Gleixner , Ludovic Barre , Julien Thierry , Sudeep Holla , Arnd Bergmann , devicetree@vger.kernel.org, Linux ARM , Linux Kernel Mailing List References: <1510649563-22975-1-git-send-email-benjamin.gaignard@linaro.org> <1510649563-22975-5-git-send-email-benjamin.gaignard@linaro.org> <44bb54e6-c9e8-4b54-d490-a1800bf6d74c@linaro.org> From: Daniel Lezcano Message-ID: <2afa343b-3a23-3352-33b3-2133678a4122@linaro.org> Date: Thu, 7 Dec 2017 17:49:55 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 07/12/2017 17:33, Benjamin Gaignard wrote: > 2017-12-07 16:27 GMT+01:00 Daniel Lezcano : >> On 14/11/2017 09:52, Benjamin Gaignard wrote: >>> The clock driving counters is at 90MHz so the maximum period >>> for 16 bis counters is around 750 ms which is a short period >>> for a clocksource. >> >> Isn't it 728us ? > > yes it is: 2^16 / 90.000.000 => 728us Ok, now I can do the connection with the previous patch. So, the real issue of all this is the 16bits clocksource is wrapping up every 728us, hence the clockevent periodically expires every ~728us to keep the timekeeping consistent. Unfortunately, the kernel has a too high overhead for this as the system is consistently processing this timer leading to a CPU time resource starvation. Is that correct ? >>> For 32 bits counters this period is close >>> 47 secondes which is more acceptable. >>> >>> This patch remove 16 bits counters support and makes sure that >>> they won't be probed anymore. >>> >>> Signed-off-by: Benjamin Gaignard >>> --- >>> drivers/clocksource/timer-stm32.c | 26 ++++++++++++-------------- >>> 1 file changed, 12 insertions(+), 14 deletions(-) >>> >>> diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c >>> index ae41a19..8173bcf 100644 >>> --- a/drivers/clocksource/timer-stm32.c >>> +++ b/drivers/clocksource/timer-stm32.c >>> @@ -83,9 +83,9 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) >>> static int __init stm32_clockevent_init(struct device_node *node) >>> { >>> struct reset_control *rstc; >>> - unsigned long max_delta; >>> - int ret, bits, prescaler = 1; >>> + unsigned long max_arr; >>> struct timer_of *to; >>> + int ret; >>> >>> to = kzalloc(sizeof(*to), GFP_KERNEL); >>> if (!to) >>> @@ -115,29 +115,27 @@ static int __init stm32_clockevent_init(struct device_node *node) >>> >>> /* Detect whether the timer is 16 or 32 bits */ >>> writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); >>> - max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); >>> - if (max_delta == ~0U) { >>> - prescaler = 1; >>> - bits = 32; >>> - } else { >>> - prescaler = 1024; >>> - bits = 16; >>> + max_arr = readl_relaxed(timer_of_base(to) + TIM_ARR); >>> + if (max_arr != ~0U) { >>> + pr_err("32 bits timer is needed\n"); >>> + ret = -EINVAL; >>> + goto deinit; >>> } >>> + >>> writel_relaxed(0, timer_of_base(to) + TIM_ARR); >>> >>> - writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); >>> + writel_relaxed(0, timer_of_base(to) + TIM_PSC); >>> writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); >>> writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); >>> writel_relaxed(0, timer_of_base(to) + TIM_SR); >>> >>> clockevents_config_and_register(&to->clkevt, >>> - timer_of_period(to), MIN_DELTA, max_delta); >>> - >>> - pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", >>> - node, bits); >>> + timer_of_period(to), MIN_DELTA, ~0U); >>> >>> return 0; >>> >>> +deinit: >>> + timer_of_exit(to); >>> err: >>> kfree(to); >>> return ret; >>> >> >> >> -- >> Linaro.org │ Open source software for ARM SoCs >> >> Follow Linaro: Facebook | >> Twitter | >> Blog >> > > > -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog