From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E290FC48BE4 for ; Thu, 27 Jun 2019 18:16:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C3E8620B7C for ; Thu, 27 Jun 2019 18:16:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="Lzkd05ca"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="iOVrGKe0" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726709AbfF0SQA (ORCPT ); Thu, 27 Jun 2019 14:16:00 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:38548 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726599AbfF0SP7 (ORCPT ); Thu, 27 Jun 2019 14:15:59 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 4B7AC60DAD; Thu, 27 Jun 2019 18:15:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1561659358; bh=Lz3k/LZ0eJkEWfeJA4dvwqIvzmvYo86ur1JDk9IAS94=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Lzkd05cadR+VcLtDFKmWEYTQr+Z/FWNMayfa1lp2IBpnHx2sogvA6WDtkLSHn4xJ/ Xg5SaKZXkLGVErGTHZ2nGVijSvYYfeUpZXw3ALAZrgsLNcDD4sknz5QtpY7CPB0OFQ 29foyOZHT/oJMontSvlBDyuZh0gWE57U0JlSdC80= Received: from blr-ubuntu-311.qualcomm.com (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan@codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id AA74760AA8; Thu, 27 Jun 2019 18:15:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1561659357; bh=Lz3k/LZ0eJkEWfeJA4dvwqIvzmvYo86ur1JDk9IAS94=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iOVrGKe0a3g9isQq9B0nO6PQcASg/n9Duxk7VJzhena/RHnH11geeWn9cixyk2mki gr0L+hMPDb463HmPsrkuYeK50k9kJ43BcWBLPNMckfYJTgmSQI2hbgrPnjpStVb/80 g4rODFOAi6S8WYjrtQU02g8lHsQ/kB3a4RedpHKw= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org AA74760AA8 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=saiprakash.ranjan@codeaurora.org From: Sai Prakash Ranjan To: Mathieu Poirier , Suzuki K Poulose , Rob Herring , devicetree@vger.kernel.org, Leo Yan , Alexander Shishkin , David Brown , Mark Rutland Cc: Rajendra Nayak , Vivek Gautam , Sibi Sankar , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Sai Prakash Ranjan Subject: [PATCHv5 1/2] dt-bindings: coresight: Change CPU phandle to required property Date: Thu, 27 Jun 2019 23:45:28 +0530 Message-Id: <2afedb941294af7ba0658496b4aca3759a4e43ff.1561659046.git.saiprakash.ranjan@codeaurora.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Do not assume the affinity to CPU0 if cpu phandle is omitted. Update the DT binding rules to reflect the same by changing it to a required property. Signed-off-by: Sai Prakash Ranjan Reviewed-by: Suzuki K Poulose --- .../devicetree/bindings/arm/coresight-cpu-debug.txt | 4 ++-- Documentation/devicetree/bindings/arm/coresight.txt | 8 +++++--- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt index 298291211ea4..f1de3247c1b7 100644 --- a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt +++ b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt @@ -26,8 +26,8 @@ Required properties: processor core is clocked by the internal CPU clock, so it is enabled with CPU clock by default. -- cpu : the CPU phandle the debug module is affined to. When omitted - the module is considered to belong to CPU0. +- cpu : the CPU phandle the debug module is affined to. Do not assume it + to default to CPU0 if omitted. Optional properties: diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 8a88ddebc1a2..fcc3bacfd8bc 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -59,6 +59,11 @@ its hardware characteristcs. * port or ports: see "Graph bindings for Coresight" below. +* Additional required property for Embedded Trace Macrocell (version 3.x and + version 4.x): + * cpu: the cpu phandle this ETM/PTM is affined to. Do not + assume it to default to CPU0 if omitted. + * Additional required properties for System Trace Macrocells (STM): * reg: along with the physical base address and length of the register set as described above, another entry is required to describe the @@ -87,9 +92,6 @@ its hardware characteristcs. * arm,cp14: must be present if the system accesses ETM/PTM management registers via co-processor 14. - * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the - source is considered to belong to CPU0. - * Optional property for TMC: * arm,buffer-size: size of contiguous buffer space for TMC ETR -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation