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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-33fed5b056dsm4181028a91.1.2025.10.27.06.29.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Oct 2025 06:29:40 -0700 (PDT) Message-ID: <2b4cd5a6-98f8-4ec6-bdac-c6c7dae84049@rivosinc.com> Date: Mon, 27 Oct 2025 14:29:29 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [External] [PATCH v7 2/5] riscv: add support for SBI Supervisor Software Events extension To: Xu Lu Cc: Paul Walmsley , Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Himanshu Chauhan , Anup Patel , Atish Patra , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Yunhui Cui References: <20250908181717.1997461-1-cleger@rivosinc.com> <20250908181717.1997461-3-cleger@rivosinc.com> Content-Language: en-US From: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 10/27/25 13:00, Xu Lu wrote: >> +void do_sse(struct sse_event_arch_data *arch_evt, struct pt_regs *regs) >> +{ >> + nmi_enter(); >> + >> + /* Retrieve missing GPRs from SBI */ >> + sbi_ecall(SBI_EXT_SSE, SBI_SSE_EVENT_ATTR_READ, arch_evt->evt_id, >> + SBI_SSE_ATTR_INTERRUPTED_A6, >> + (SBI_SSE_ATTR_INTERRUPTED_A7 - SBI_SSE_ATTR_INTERRUPTED_A6) + 1, >> + arch_evt->interrupted_phys, 0, 0); >> + >> + memcpy(®s->a6, &arch_evt->interrupted, sizeof(arch_evt->interrupted)); >> + >> + sse_handle_event(arch_evt, regs); >> + >> + /* >> + * The SSE delivery path does not uses the "standard" exception path >> + * (see sse_entry.S) and does not process any pending signal/softirqs >> + * due to being similar to a NMI. >> + * Some drivers (PMU, RAS) enqueue pending work that needs to be handled >> + * as soon as possible by bottom halves. For that purpose, set the SIP >> + * software interrupt pending bit which will force a software interrupt >> + * to be serviced once interrupts are reenabled in the interrupted >> + * context if they were masked or directly if unmasked. >> + */ >> + csr_set(CSR_IP, IE_SIE); > IE_SIE may not always be enabled in CSR_IE(for example when we disable > CONFIG_ACLINT_SSWI and use imsic for ipi). Maybe we should send ipi to > the current cpu here. Hi Xu, Indeed, that's a good catch. Sending an IPI will be more generic. Thanks, ClĂ©ment > > Best regards, > Xu Lu