From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4944CC43381 for ; Thu, 28 Mar 2019 12:40:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2072F2173C for ; Thu, 28 Mar 2019 12:40:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727954AbfC1Mkd (ORCPT ); Thu, 28 Mar 2019 08:40:33 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:55286 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727586AbfC1Mkc (ORCPT ); Thu, 28 Mar 2019 08:40:32 -0400 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id BB45A4A01DC6FFD809E5; Thu, 28 Mar 2019 20:40:29 +0800 (CST) Received: from [127.0.0.1] (10.202.227.238) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.408.0; Thu, 28 Mar 2019 20:40:20 +0800 Subject: Re: [PATCH 3/4] arm_pmu: acpi: spe: Add initial MADT/SPE probing To: Jeremy Linton , References: <20190326223938.5365-1-jeremy.linton@arm.com> <20190326223938.5365-4-jeremy.linton@arm.com> CC: , , , , , , , , , , From: John Garry Message-ID: <2b53e957-6d36-fdfe-20e4-1664108c07ef@huawei.com> Date: Thu, 28 Mar 2019 12:40:12 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 In-Reply-To: <20190326223938.5365-4-jeremy.linton@arm.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.202.227.238] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 26/03/2019 22:39, Jeremy Linton wrote: > ACPI 6.3 adds additional fields to the MADT GICC > structure to describe SPE PPI's. We pick these out > of the cached reference to the madt_gicc structure > similarly to the core PMU code. We then create a platform > device referring to the IRQ and let the user/module loader > decide whether to load the SPE driver. > > Signed-off-by: Jeremy Linton > --- > arch/arm64/include/asm/acpi.h | 3 ++ > drivers/perf/arm_pmu_acpi.c | 69 +++++++++++++++++++++++++++++++++++ > 2 files changed, 72 insertions(+) > > diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h > index 7628efbe6c12..d10399b9f998 100644 > --- a/arch/arm64/include/asm/acpi.h > +++ b/arch/arm64/include/asm/acpi.h > @@ -41,6 +41,9 @@ > (!(entry) || (entry)->header.length < ACPI_MADT_GICC_MIN_LENGTH || \ > (unsigned long)(entry) + (entry)->header.length > (end)) > > +#define ACPI_MADT_GICC_SPE (ACPI_OFFSET(struct acpi_madt_generic_interrupt, \ > + spe_interrupt) + sizeof(u16)) > + > /* Basic configuration for ACPI */ > #ifdef CONFIG_ACPI > pgprot_t __acpi_get_mem_attribute(phys_addr_t addr); > diff --git a/drivers/perf/arm_pmu_acpi.c b/drivers/perf/arm_pmu_acpi.c > index 0f197516d708..a2418108eab2 100644 > --- a/drivers/perf/arm_pmu_acpi.c > +++ b/drivers/perf/arm_pmu_acpi.c > @@ -74,6 +74,73 @@ static void arm_pmu_acpi_unregister_irq(int cpu) > acpi_unregister_gsi(gsi); > } > > +static struct resource spe_resources[] = { > + { > + /* irq */ > + .flags = IORESOURCE_IRQ, > + } > +}; > + > +static struct platform_device spe_dev = { > + .name = "arm,spe-v1", > + .id = -1, > + .resource = spe_resources, > + .num_resources = ARRAY_SIZE(spe_resources) > +}; > + > +/* > + * For lack of a better place, It seems that the kernel Image size can now increase due to this part of SPE support even if ARM_SPE_PMU config is disabled. And I don't even think that ARM_SPE_PMU depends on ARM_PMU (which ARM_PMU_ACPI depends on). Thanks, John hook the normal PMU MADT walk > + * and create a SPE device if we detect a recent MADT with > + * a homogeneous PPI mapping. > + */ > +static int arm_spe_acpi_parse_irqs(void) > +{ > + int cpu, ret, irq; > + int hetid; > + u16 gsi = 0; > + bool first = true; > + > + struct acpi_madt_generic_interrupt *gicc; > + > + /* > + * sanity check all the GICC tables for the same interrupt number > + * for now we only support homogeneous ACPI/SPE machines. > + */ > + for_each_possible_cpu(cpu) { > + gicc = acpi_cpu_get_madt_gicc(cpu); > + > + if (gicc->header.length < ACPI_MADT_GICC_SPE) > + return -ENODEV; > + if (first) { > + gsi = gicc->spe_interrupt; > + if (!gsi) > + return -ENODEV; > + hetid = find_acpi_cpu_topology_hetero_id(cpu); > + first = false; > + } else if ((gsi != gicc->spe_interrupt) || > + (hetid != find_acpi_cpu_topology_hetero_id(cpu))) { > + pr_warn("ACPI: SPE must be homogeneous\n"); > + return -EINVAL; > + } > + } > + > + irq = acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, > + ACPI_ACTIVE_HIGH); > + if (irq < 0) { > + pr_warn("ACPI: SPE Unable to register interrupt: %d\n", gsi); > + return irq; > + } > + > + spe_resources[0].start = irq; > + ret = platform_device_register(&spe_dev); > + if (ret < 0) { > + pr_warn("ACPI: SPE: Unable to register device\n"); > + acpi_unregister_gsi(gsi); > + } > + > + return ret; > +} > + > static int arm_pmu_acpi_parse_irqs(void) > { > int irq, cpu, irq_cpu, err; > @@ -279,6 +346,8 @@ static int arm_pmu_acpi_init(void) > if (acpi_disabled) > return 0; > > + arm_spe_acpi_parse_irqs(); /* failures are expected */ > + > ret = arm_pmu_acpi_parse_irqs(); > if (ret) > return ret; >