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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODAxMDAyNyBTYWx0ZWRfX2Zjqtetow6lQ WIU3eyNjIhdZa0gJ3e6bWm638AswGMaUngvPPyLwgZF3Ix9uzKxd1PFtdeW4E0QbViXBdLzh+U7 WgNcnAN/kZHNQTHBK2ZlenSOKb95oLuI55DUB0Y0E4r3ZcO6HC++mGU33IXoYWW7GuqG5xKhtZZ 4iFShL7QWThvxj2kX8LUw1H6/iRkhzrCAq+cDg/yEbBIJymFw7KKvCmkHtm0/fBlSu9HTgJkSMj FmFKhfiqYVSJ5EfzvVHGba5Iuzr4lN7DLaEM3k3p6ouc/HTevq5N/FPgv3sAt2coP/+ZED4l0RJ tVHxEfvXjOdtdpG5wNrkjvtTipC5odUoDsiNC+e9ogq3+zGwLqYcaT2ZKhuXxjAa/T+QXfGGUkF NO7AKXwiLzYvWdKfeM82DznWFNYotHw1xt1eufWE2lw3o2uI2QXG1z8OLaFwzgo0obx9uU07 X-Authority-Analysis: v=2.4 cv=TqLmhCXh c=1 sm=1 tr=0 ts=688c41ac cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=-exJQLPiCZ_865CLFvcA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-ORIG-GUID: UHuNXO_ffQ74eu8CqvwlnZuuDiZD_E6- X-Proofpoint-GUID: UHuNXO_ffQ74eu8CqvwlnZuuDiZD_E6- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-31_04,2025-07-31_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 adultscore=0 spamscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2508010027 On 7/29/2025 4:19 PM, Konrad Dybcio wrote: > On 7/29/25 12:48 PM, Dmitry Baryshkov wrote: >> On Tue, Jul 29, 2025 at 11:12:41AM +0530, Taniya Das wrote: >>> Add support for Global clock controller for Glymur platform. >>> >>> Signed-off-by: Taniya Das >>> --- >>> drivers/clk/qcom/Kconfig | 9 + >>> drivers/clk/qcom/Makefile | 1 + >>> drivers/clk/qcom/gcc-glymur.c | 8623 +++++++++++++++++++++++++++++++++++++++++ >>> 3 files changed, 8633 insertions(+) >>> >>> +static void clk_glymur_regs_configure(struct device *dev, struct regmap *regmap) >>> +{ >>> + int ret; >>> + >>> + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, >>> + ARRAY_SIZE(gcc_dfs_clocks)); >> >> Why are you doing this manually instead of using >> qcom_cc_driver_data.dfs_rcgs ? > > I guess that has been merged last week or so, so yeah, please rebase > Yes, sure I will rebase on the latest changes. -- Thanks, Taniya Das