Re: [PATCH RFC 1/3] arm64: dts: qcom: nord: Add SoCCP remoteproc DT support for Nord

[Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>]

On 10/16/2026 2:35 PM, Abel Vesa wrote:
> On 26-10-16 11:09:54, Anurag Pateriya wrote:
>> Add the SoCCP (System on Chip Control Processor) remoteproc node and
>> its SMP2P configuration at the SoC level in nord.dtsi, and wire up
>> the clock and power-domain dependencies shared by all Nord embedded
>> variants in nord-embedded.dtsi.
>>
>> Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
>> ---
>>   arch/arm64/boot/dts/qcom/nord-embedded.dtsi |   9 ++
>>   arch/arm64/boot/dts/qcom/nord.dtsi          | 126 ++++++++++++++++++++++++++++
>>   2 files changed, 135 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
>> index 6dc4c871f41e..e21b9ba480f5 100644
>> --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
>> @@ -430,6 +430,15 @@ &remoteproc_cdsp3 {
>>   			     "nsp";
>>   };
>>   
>> +&remoteproc_soccp {
>> +	clocks = <&rpmhcc RPMH_CXO_CLK>;
>> +	clock-names = "xo";
>> +	power-domains = <&rpmhpd RPMHPD_CX>,
>> +			<&rpmhpd RPMHPD_MX>;
>> +	power-domain-names = "cx",
>> +			     "mx";
>> +};
>> +
>>   &spi0 {
>>   	clocks = <&segcc SE_GCC_QUPV3_WRAP0_S0_CLK>;
>>   	clock-names = "se";
>> diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
>> index dfbbaf94a7ae..53c594281f6b 100644
>> --- a/arch/arm64/boot/dts/qcom/nord.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/nord.dtsi
>> @@ -1029,6 +1029,28 @@ smp2p_cdsp3_in: slave-kernel {
>>   		};
>>   	};
>>   
>> +	smp2p-soccp {
>> +		compatible = "qcom,smp2p";
>> +		interrupts-extended = <&ipcc0 IPCC_MPROC_SOCCP
>> +					      IPCC_MPROC_SIGNAL_SMP2P
>> +					      IRQ_TYPE_EDGE_RISING>;
>> +		mboxes = <&ipcc0 IPCC_MPROC_SOCCP IPCC_MPROC_SIGNAL_SMP2P>;
>> +		qcom,smem = <617>, <616>;
>> +		qcom,local-pid = <0>;
>> +		qcom,remote-pid = <19>;
>> +
>> +		smp2p_soccp_out: master-kernel {
>> +			qcom,entry-name = "master-kernel";
>> +			#qcom,smem-state-cells = <1>;
>> +		};
>> +
>> +		smp2p_soccp_in: slave-kernel {
>> +			qcom,entry-name = "slave-kernel";
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +		};
>> +	};
>> +
>>   	soc: soc@0 {
>>   		compatible = "simple-bus";
>>   		#address-cells = <2>;
>> @@ -1587,6 +1609,110 @@ uart13: serial@a98000 {
>>   			};
>>   		};
>>   
>> +		remoteproc_soccp: remoteproc@d00000 {
>> +			compatible = "qcom,nord-soccp-pas";
>> +			reg = <0x0 0x00d00000 0x0 0x200000>;
>> +
>> +			interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
>> +					      <&smp2p_soccp_in 0 IRQ_TYPE_EDGE_RISING>,
>> +					      <&smp2p_soccp_in 1 IRQ_TYPE_EDGE_RISING>,
>> +					      <&smp2p_soccp_in 2 IRQ_TYPE_EDGE_RISING>,
>> +					      <&smp2p_soccp_in 3 IRQ_TYPE_EDGE_RISING>,
>> +					      <&smp2p_soccp_in 9 IRQ_TYPE_EDGE_RISING>;
>> +			interrupt-names = "wdog",
>> +					  "fatal",
>> +					  "ready",
>> +					  "handover",
>> +					  "stop-ack",
>> +					  "pong";
>> +
>> +			memory-region = <&soccp_mem>;
>> +
>> +			qcom,smem-states = <&smp2p_soccp_out 0>,
>> +					   <&smp2p_soccp_out 8>;
>> +			qcom,smem-state-names = "stop",
>> +						"ping";
>> +
>> +			status = "disabled";
>> +
>> +			glink-edge {
>> +				interrupts-extended = <&ipcc0 IPCC_MPROC_SOCCP
>> +							      IPCC_MPROC_SIGNAL_GLINK_QMP
>> +							      IRQ_TYPE_EDGE_RISING>;
>> +				mboxes = <&ipcc0 IPCC_MPROC_SOCCP
>> +						 IPCC_MPROC_SIGNAL_GLINK_QMP>;
>> +				qcom,remote-pid = <19>;
>> +				label = "soccp";
>> +			};
>> +		};
>> +
>> +		bwmon_cluster2: pmu@1014400 {
>> +			reg = <0x0 0x01014400 0x0 0x600>;
>> +			interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>;
>> +			operating-points-v2 = <&bwmon_cluster_opp_table>;
>> +		};
> 
> This isn't supposed to be part of this patch, right?
> 
> Same for the ones below.

Yes. I will remove these changes in next version.

> 
>> +
>> +		bwmon_cluster1: pmu@1015400 {
>> +			reg = <0x0 0x01015400 0x0 0x600>;
>> +			interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>;
>> +			operating-points-v2 = <&bwmon_cluster_opp_table>;
>> +		};
>> +
>> +		bwmon_cluster0: pmu@1016400 {
>> +			reg = <0x0 0x01016400 0x0 0x600>;
>> +			interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> +			operating-points-v2 = <&bwmon_cluster_opp_table>;
>> +
>> +			bwmon_cluster_opp_table: opp-table {
>> +				compatible = "operating-points-v2";
>> +
>> +				opp-0 {
>> +					opp-peak-kBps = <800000>;
>> +				};
>> +
>> +				opp-1 {
>> +					opp-peak-kBps = <2188800>;
>> +				};
>> +
>> +				opp-2 {
>> +					opp-peak-kBps = <5414400>;
>> +				};
>> +
>> +				opp-3 {
>> +					opp-peak-kBps = <6220800>;
>> +				};
>> +
>> +				opp-4 {
>> +					opp-peak-kBps = <6835200>;
>> +				};
>> +
>> +				opp-5 {
>> +					opp-peak-kBps = <7603200>;
>> +				};
>> +
>> +				opp-6 {
>> +					opp-peak-kBps = <8371200>;
>> +				};
>> +
>> +				opp-7 {
>> +					opp-peak-kBps = <9657600>;
>> +				};
>> +
>> +				opp-8 {
>> +					opp-peak-kBps = <10944000>;
>> +				};
>> +
>> +				opp-9 {
>> +					opp-peak-kBps = <12748800>;
>> +				};
>> +
>> +				opp-10 {
>> +					opp-peak-kBps = <14745600>;
>> +				};
>> +			};
>> +		};
>> +
>>   		rng: rng@10c3000 {
>>   			compatible = "qcom,nord-trng",
>>   				     "qcom,trng";
>>
>> -- 
>> 2.43.0
>>

Thanks,
Anurag