From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933253AbcIEN2m (ORCPT ); Mon, 5 Sep 2016 09:28:42 -0400 Received: from mx1.redhat.com ([209.132.183.28]:34238 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932257AbcIEN2j (ORCPT ); Mon, 5 Sep 2016 09:28:39 -0400 Subject: Re: [PATCH] KVM: nVMX: expose INS/OUTS information support To: Jan Dakinevich , kvm@vger.kernel.org References: <1473013395-12214-1-git-send-email-jan.dakinevich@gmail.com> Cc: rkrcmar@redhat.com, linux-kernel@vger.kernel.org, ynorov@caviumnetworks.com From: Paolo Bonzini Message-ID: <2bb16b3e-90c2-0d6d-cdf3-81addb170a7e@redhat.com> Date: Mon, 5 Sep 2016 15:27:38 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: <1473013395-12214-1-git-send-email-jan.dakinevich@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Mon, 05 Sep 2016 13:27:42 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04/09/2016 20:23, Jan Dakinevich wrote: > Expose the feature to L1 hypervisor if host CPU supports it, since > certain hypervisors requires it for own purposes. > > According to Intel SDM A.1, if CPU supports the feature, > VMX_INSTRUCTION_INFO field of VMCS will contain detailed information > about INS/OUTS instructions handling. This field is already copied to > VMCS12 for L1 hypervisor (see prepare_vmcs12 routine) independently > feature presence. > > Signed-off-by: Jan Dakinevich > --- > arch/x86/kvm/vmx.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c > index a4bb2bd..4fd22a6 100644 > --- a/arch/x86/kvm/vmx.c > +++ b/arch/x86/kvm/vmx.c > @@ -939,6 +939,7 @@ static DEFINE_SPINLOCK(vmx_vpid_lock); > static struct vmcs_config { > int size; > int order; > + u32 basic_cap; > u32 revision_id; > u32 pin_based_exec_ctrl; > u32 cpu_based_exec_ctrl; > @@ -1215,6 +1216,11 @@ static inline bool cpu_has_vmx_ple(void) > SECONDARY_EXEC_PAUSE_LOOP_EXITING; > } > > +static inline bool cpu_has_vmx_basic_inout(void) > +{ > + return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT); > +} > + > static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) > { > return flexpriority_enabled && lapic_in_kernel(vcpu); > @@ -2877,6 +2883,8 @@ static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) > *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS | > ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) | > (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT); > + if (cpu_has_vmx_basic_inout()) > + *pdata |= VMX_BASIC_INOUT; > break; > case MSR_IA32_VMX_TRUE_PINBASED_CTLS: > case MSR_IA32_VMX_PINBASED_CTLS: > @@ -3458,6 +3466,7 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) > > vmcs_conf->size = vmx_msr_high & 0x1fff; > vmcs_conf->order = get_order(vmcs_config.size); > + vmcs_conf->basic_cap = vmx_msr_high; Bits 32-44 are already stored in vmcs_conf->size, so please make this "vmx_msr_high & ~0x1fff". Otherwise looks fine! Paolo > vmcs_conf->revision_id = vmx_msr_low; > > vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; >