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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ea0cda9d8fsm731205ad.14.2026.10.18.23.45.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 18 Oct 2026 23:45:42 -0700 (PDT) Message-ID: <2bb63bef-b1b5-487c-98de-7cb5fa9b6758@oss.qualcomm.com> Date: Mon, 19 Oct 2026 14:45:34 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/8] dt-bindings: arm: Add MPAM MSC binding To: Rob Herring Cc: James Morse , Shanker Donthineni , Ben Horgan , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Greg Kroah-Hartman , "Rafael J. Wysocki" , Danilo Krummrich , Reinette Chatre , Fenghua Yu , Jonathan Cameron , Bjorn Andersson , Konrad Dybcio , Gavin Shan , Andre Przywara , Drew Fustini , =?UTF-8?Q?Ilpo_J=C3=A4rvinen?= , Shaopeng Tan , trilok.soni@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, ganapatrao.kulkarni@oss.qualcomm.com, Srivathsa L Rao , Huang Yiwei , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, driver-core@lists.linux.dev, devicetree@vger.kernel.org References: <20261008-mpam-resctrl-dt-knp-support-v3-0-35196c2b43bf@oss.qualcomm.com> <20261008-mpam-resctrl-dt-knp-support-v3-3-35196c2b43bf@oss.qualcomm.com> <20261008212736.GB1318789-robh@kernel.org> <2eddfb6d-c622-4d72-827e-aed685e72b9c@oss.qualcomm.com> <51bc6576-7e52-4685-b7b2-a355c2b7e1ae@oss.qualcomm.com> <20261015193639.GE5059-robh@kernel.org> Content-Language: en-US From: Yin Li In-Reply-To: <20261015193639.GE5059-robh@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE5MDAyNiBTYWx0ZWRfX9F0LEHx1JIRw BFhO0pVgfEL+j6A/YPf4f1i++aTRrk2NPj22nAp8l++qDgEP5b5Gt+S/ufsKTeOInbivwmIfYZ+ o6zhuqU0NJpP0Vgnv9c1zJUE11YB2N0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE5MDAyNiBTYWx0ZWRfX0TZbIYdnajs0 dK/Sqsx3RJZAL/nYFSnB+TI3BOcIa4MHiiOJXV9Nr2FpUiFCvT6SRXTUtsTCF2cOUGa/4uY72sA GLC1Fh5VxF0fOxZl+s1/MTno0kRrdymt9ycLe0hNnDCz86B5h15gL/8uRqs2eeV6nk33Mrjrgfd IOOdSBYpx1HoLdBwngSWvjNqiPGF3BVHDogrRSQUqB0uV4a3MiuqgMKwSP5wCr/25d8gU5+T4/y Oo1pjtysreHVXvTWCV7qg0EPuOXyUl2aCQ6q7FSPMXtRcI0XM+HZ6Q0Kcuvx3W9IuGDeSk57Tj3 gypL1rNu9a2j2pwWcvtZi1t0EDq6GLfyhyaYfoXGC0BSLPF+MaJ7EvD+iYaakSSJWZcsphfTks1 V/KYf4gShWVifTqxTlS0IPMVr0pB4tTtLNEErY2XjOm8S4heEl7dCe69BizaI8Z76OS+G6fX8sh iZOB1HpE7AniJK9uoAw== X-Proofpoint-ORIG-GUID: XV2c1TFmr2GKfIEETN04HddrhXx6dGtB X-Proofpoint-GUID: XV2c1TFmr2GKfIEETN04HddrhXx6dGtB X-Authority-Analysis: v=2.4 cv=RYMFmFtv c=1 sm=1 tr=0 ts=6ad5bc98 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=gEfo2CItAAAA:8 a=7CQSdrXTAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=2vh7TcXBQbIRG-HjRUIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 a=sptkURWiP4Gy88Gu7hUp:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-19_02,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 impostorscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 bulkscore=0 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610190026 On 10/16/2026 3:36 AM, Rob Herring wrote: > On Mon, Oct 12, 2026 at 06:24:06PM +0800, Yin Li wrote: >> >> >> On 10/12/2026 3:05 PM, Yin Li wrote: >>> >>> >>> On 10/9/2026 5:27 AM, Rob Herring wrote: >>>> On Thu, Oct 08, 2026 at 02:41:12PM +0800, Yin Li wrote: >>>>> From: Rob Herring >>>>> >>>>> The binding is designed around the assumption that an MSC will be a >>>>> sub-block of something else such as a memory controller, cache >>>>> controller, >>>>> or IOMMU. However, it's certainly possible a design does not have that >>>>> association or has a mixture of both, so the binding illustrates >>>>> how we can >>>>> support that with RIS child nodes. >>>>> >>>>> A key part of MPAM is we need to know about all of the MSCs in >>>>> the system >>>>> before it can be enabled. This drives the need for the genericish >>>>> 'arm,mpam-msc' compatible. Though we can't assume an MSC is accessible >>>>> until a h/w specific driver potentially enables the h/w. >>>>> >>>>> Cc: James Morse >>>>> Signed-off-by: Rob Herring >>>>> Signed-off-by: James Morse >>>>> [ Yin Li and Huang Yiwei: use oneOf for the compatible to allow both >>>>>    standalone arm,mpam-msc and the two-item combination; fix >>>>> schema field >>>>>    order, type constraints and yamllint spacing; fix example reg >>>>> addresses, >>>>>    add arm,mpam-device phandle and remove TODO comment ] >>>>> Co-developed-by: Huang Yiwei >>>>> Signed-off-by: Huang Yiwei >>>>> Signed-off-by: Yin Li >>>>> --- >>>>>   .../devicetree/bindings/arm/arm,mpam-msc.yaml      | 202 >>>>> ++++++++++ +++++++++++ >>>>>   1 file changed, 202 insertions(+) >>>>> >>>>> diff --git >>>>> a/Documentation/devicetree/bindings/arm/arm,mpam-msc.yaml >>>>> b/Documentation/devicetree/bindings/arm/arm,mpam-msc.yaml >>>>> new file mode 100644 >>>>> index 000000000000..3c7b13a23ff2 >>>>> --- /dev/null >>>>> +++ b/Documentation/devicetree/bindings/arm/arm,mpam-msc.yaml >>>>> @@ -0,0 +1,202 @@ >>>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >>>>> +%YAML 1.2 >>>>> +--- >>>>> +$id: http://devicetree.org/schemas/arm/arm,mpam-msc.yaml# >>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>>> + >>>>> +title: Arm Memory System Resource Partitioning and Monitoring (MPAM) >>>>> + >>>>> +maintainers: >>>>> +  - Rob Herring >>>>> + >>>>> +description: | >>>>> +  The Arm MPAM specification can be found here: >>>>> + >>>>> +  https://developer.arm.com/documentation/ddi0598/latest >>>>> + >>>>> +properties: >>>>> +  compatible: >>>>> +    oneOf: >>>>> +      - const: arm,mpam-msc                   # Further details >>>>> are discoverable >>>>> +      - items: >>>>> +          - const: arm,mpam-memory-controller-msc >>>> >>>> Why do we need this? >>>> >>> >>> Hi Rob, >>> >>> Thanks for the review. >>> >>> The 'arm,mpam-memory-controller-msc' compatible is needed because, >>> unlike cache MSCs, memory controller MSCs cannot rely on the parent node >>> to identify the resource type. >>> >>> Cache controllers universally carry a 'cache' compatible, so the driver >>> can recognise any cache parent and derive the cache ID from standard >>> properties. No equivalent convention exists for memory controllers, and >>> the component ID comes from the MSC's own 'numa-node-id' rather than the >>> parent, so there is no parent attribute to rely on. >>> >> >> Hi Rob, >> >> As a follow-up to my previous reply: >> Whatever the outcome of the discussion on "arm_mpam: Add support for >> memory controller MSC on DT platforms", we will keep the binding and >> driver support consistent. If it's dropped, the >> 'arm,mpam-memory-controller-msc' compatible, 'numa-node-id' property, and >> the memory controller example will be removed together. > > Which parts are you actually using/needing and not using? If you don't > need RIS support, for example, we should drop it. > Hi Rob, The Kaanapali DTS only uses 'arm,mpam-msc' nested under a cache node, deriving type and affinity from the parent — following your earlier suggestion. No RIS child nodes are used. However, this is not universally applicable. On most platforms, L2 cache nodes sit under CPU nodes, which do not provide an MMIO address space. Nesting an MSC there causes address translation failures. The Kaanapali DNM patch moves the cache nodes out of the CPU to work around this, which also has the benefit of making the MSC-cache parent relationship explicit in the device tree — though this is still an artificial arrangement for demonstration purposes. In fact, if Kaanapali supported direct MMIO access to the MPAM registers, it would also need to place the MSC independently and use RIS with 'arm,mpam-device' to point to the L2 cache node under the CPU — the same approach required on any platform where the cache topology cannot be modified. Therefore, apart from the memory controller MSC support, we believe the remaining parts — including RIS — are needed on the Kaanapali platform. Thanks, Yin > Rob -- Thx and BRs, Yin