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definitions=main-2602230140 X-Authority-Analysis: v=2.4 cv=La0xKzfi c=1 sm=1 tr=0 ts=699c7ebf cx=c_pps a=XiAAW1AwiKB2Y8Wsi+sD2Q==:117 a=XiAAW1AwiKB2Y8Wsi+sD2Q==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=z/mQ4Ysz8XfWz/Q5cLBRGdckG28=:19 a=lCpzRmAYbLLaTzLvsPZ7Mbvzbb8=:19 a=xqWC_Br6kY4A:10 a=8nJEP1OIZ-IA:10 a=HzLeVaNsDn8A:10 a=GoEa3M9JfhUA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=hFem9kaWIBW115rplIAA:9 a=3ZKOabzyN94A:10 a=wPNLvfGTeEIA:10 X-Proofpoint-ORIG-GUID: NYNCOmZIwJZPScaIhze-gwvYYEUT32Lo X-Proofpoint-GUID: NYNCOmZIwJZPScaIhze-gwvYYEUT32Lo X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjIzMDE0MCBTYWx0ZWRfX/uF9QuRYMHbz ErmNKfgYy1eI3RvCU2GLNO7XnDz2Y3rGjSQn8mvXNZkdp39ART/043CNLTp0wfn3qWqtP4pAdrf vXPvdaq7CHYI0s+ceHUmD1wK4TlGuMpib+gSCN/ImcpZZ0fdh9mu4sX+hiMSA0YOTu5qlGwroq4 HS5iP60LzzyucqajXI+8JUZ5XRVLhHpGq/nE4jxebmJxj6QbQC426moNV+M+bcy9WCyxT0eITTd Jsx5kECJnDVYZO8H/cXJOW0aEjP2xdXQh8AcjFs9xcMwo57ojrrl3TMpFQ/YezuFX7wAMd8104A RU04sVIfo3Ige7CdRhTWEt+ptMWgNP2w3XzIrIzMJrf09JPRJBlxAqoobivXEXKXUDgm2OUiz+B nCb/dsIeMCQOXHyvCn0pP+ZBaKKjpr6iwwrS7o2BNnYN0fzhmUR079+ER26F5RoIMR05BX2KFvN feZdPH9ZpznaMnlxBNg== On Mon, Feb 23, 2026 at 04:31:56PM +0100, David Hildenbrand (Arm) wrote: > On 2/23/26 16:14, Dave Hansen wrote: > > On 2/23/26 03:27, David Hildenbrand (Arm) wrote: > > ... > > > > BTW, x86-64 SysV ABI allows for 64k page size: > > > > > > > >     Systems are permitted to use any power-of-two page size between > > > >     4KB and 64KB, inclusive. > > > > > > > > But it doesn't work in practice. > > > > > > Even in well controlled environments you would run in a hyperscaler? > > > > I think what Kirill is trying to say is that "it breaks userspace". ;) > > Yes. Probably similar to Intel proposing an actual 64k page size. Expected. > :) > > > > > A hyperscaler (or other "embedded" environment) might be willing or able > > to go fix up userspace breakage. I would suspect our high frequency > > trading friends would be all over this if it shaved a microsecond off > > their receive times. > > > > The more important question is what it breaks and how badly it breaks > > things. 5-level paging, for instance, broke some JITs that historically > > used the new (>48) upper virtual address bits for metadata. The gains > > from 5-level paging were big enough and the userspace breakage was > > confined and fixable enough that 5-level paging was viable. > > > > I'm not sure which side a larger base page side will fall on, though. Is > > it going to be an out-of-tree hack that a few folks use, or will it be > > more like 5-level paging and be good enough that it goes into mainline? > > Just thinking about VMAs spanning partial pages makes me shiver. Or A single > page spanning multiple VMAs. Yeah agree, we're not doing this. It's already a nightmare to deal with per-page anonexclusive vs. per-folio pretty much everything else, and we shouldn't have allowed that to be a thing, but now we have to live with it. > > I haven't seen the code yet, but I am certain that I will not like it. If the code tries to implement anything that even resembles some sub-base-page metadata then that's just not something that's going to land. Handling VMA vs. folio state coherently is _already_ painful and difficult. Piling on more complexity because we theoretically could feels rather along the lines of 'let's just keep adding features and not worrying about where we end up', which is I think a bit of an anti-pattern in the kernel in general. > > I'm happy to be proven wrong :) Sure me also if I'm missing something, but what's discussed here is... worrying. > > -- > Cheers, > > David Thanks, Lorenzo