From: Sandipan Das <sandipan.das@amd.com>
To: Luka Absandze <absandze@amazon.de>,
peterz@infradead.org, mingo@redhat.com, acme@kernel.org,
namhyung@kernel.org, tglx@kernel.org, bp@alien8.de,
dave.hansen@linux.intel.com, x86@kernel.org, yaoz@meta.com,
dwmw2@infradead.org
Cc: kim.phillips@amd.com, kvm@vger.kernel.org,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] perf/x86/amd: Reject AMD Merge event as a countable event
Date: Mon, 21 Sep 2026 10:39:05 +0530 [thread overview]
Message-ID: <2bdad6ef-ed83-4a28-8717-61ac043739b7@amd.com> (raw)
In-Reply-To: <20260916123315.89042-1-absandze@amazon.de>
On 16-09-2026 18:03, Luka Absandze wrote:
> AMD event select 0xFFF (Merge) is the hardware control encoding used by
> Large Increment per Cycle (LIPC) pairs. When written into an odd
> counter's PerfCtl it turns that counter into the upper 16 bits of a
> 64-bit merged accumulator; any subsequent arming write (-(2^47-1)) is
> silently truncated to its low 16 bits, while hwc->prev_count retains the
> full value.
>
> This is particularly problematic with a KVM guest, which will program
> the Merge encoding into its own odd vPMC as a normal part of scheduling
> a LIPC event. KVM intercepts that write and faithfully forwards it to
> the host as a raw event carrying the Merge encoding, where it is
> accepted as an ordinary countable event. Once a counter's PerfCtl holds
> the Merge encoding, every later user of that counter gets a first delta
> inflated by 2^47
>
> Reject Merge (AMD_MERGE_EVENT) in amd_core_hw_config() so it cannot be
> submitted as a user-visible event. The pair mechanism programs it
> itself via x86_pmu.perf_ctr_pair_en; nothing else should do so.
>
> Fixes: 5738891229a2 ("perf/x86/amd: Add support for Large Increment per Cycle Events")
> Reported-by: Yao Zhou <yaoz@meta.com>
> Signed-off-by: Luka Absandze <absandze@amazon.de>
> ---
> arch/x86/events/amd/core.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
> index 49b6b8fce566..cb655c751e5b 100644
> --- a/arch/x86/events/amd/core.c
> +++ b/arch/x86/events/amd/core.c
> @@ -380,8 +380,12 @@ static int amd_core_hw_config(struct perf_event *event)
> else if (event->attr.exclude_guest)
> event->hw.config |= AMD64_EVENTSEL_HOSTONLY;
>
> - if ((x86_pmu.flags & PMU_FL_PAIR) && amd_is_pair_event_code(&event->hw))
> - event->hw.flags |= PERF_X86_EVENT_PAIR;
> + if (x86_pmu.flags & PMU_FL_PAIR) {
> + if ((event->hw.config & AMD64_EVENTSEL_EVENT) == AMD_MERGE_EVENT)
> + return -EINVAL;
> + if (amd_is_pair_event_code(&event->hw))
> + event->hw.flags |= PERF_X86_EVENT_PAIR;
> + }
>
> if (has_branch_stack(event))
> return static_call(amd_pmu_branch_hw_config)(event);
Reviewed-by: Sandipan Das <sandipan.das@amd.com>
prev parent reply other threads:[~2026-09-21 5:09 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-16 12:33 Luka Absandze
2026-09-16 15:04 ` Borislav Petkov
2026-09-21 5:09 ` Sandipan Das [this message]
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